MH28S72PJG -7 General Description
The MH28S72PJG is 134,217,728 - word x 72-bit Synchronous DRAM stacked structural module. This consist of t hirty-six industry standard 64M x 4 Synchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual inline package prov ides any application where high densities and large of quantities memory are required.
This is a socket-type memory module ,suitable f or
easy interchange or addition of module
MH28S72PJG -7 Maximum Ratings
MH28S72PJG -7 Features
·Utilizes industry standard 64M X 4 Synchronous DRAMs in TSOP package , industry standard Resister in TSSOP package , and industry standard PLL in TSSOP package.
·Single 3.3V +/- 0.3V supply
·Burst length 1/2/4/8/Full Page (programmable)
·Burst type sequential / interleave (programmable)
·Column access random
·Burst Write / Single Write (programmable)
·Auto precharge / Auto bank precharge controlled by A10
·Auto refresh and Self refresh
·LVTTL Interface
·8192 refresh cycles every 64ms
MH28S72PJG -7 Typical Application
Main memory unit for computers, Microcomputer memory
MH203
PDF/DataSheet Download

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- MITSUBISHI [Mitsubishi Electric Semiconductor]
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- 8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
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- ·MH28S72PJG-5
- MITSUBISHI [Mitsubishi Electric Semiconductor]
- 9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
- 977449 KB

- ·MH28S72PJG-6
- MITSUBISHI [Mitsubishi Electric Semiconductor]
- 9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
- 977449 KB

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