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Part Number: MH32S72PHB-6

 

 

 

 

Description: The MH32S72PHB is 33554432 - word x 72-bit Synchronous DRAM module. This consist of eighteen industry standard 16M x 8 ...


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MH32S72PHB-6 General Description


The MH32S72PHB is 33554432 - word x 72-bit Synchronous DRAM module. This consist of eighteen industry standard 16M x 8 Synchronous DRAMs in TSOP.

The TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required.

This is a socket-type memory module ,suitable for easy interchange or addition of module.

MH32S72PHB-6 Maximum Ratings

Symbol Parameter Condition Ratings Unit
Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V
VI Input Voltage with respect to Vss -0.5 ~ 4.6 V
VO Output Voltage with respect to Vss -0.5 ~ 4.6 V
IO Output Current   50 mA
Pd Power Dissipation Ta=25C 18 W
Topr Operating Temperature   0 ~ 70 C
Tstg Storage Temperature   -45 ~ 100 C

MH32S72PHB-6 Features

· Utilizes industry standard 16M X 8 Synchronous DRAMs in TSOP package
· Single 3.3V +/- 0.3V supply
· Max.Clock frequency 133MHz
· Fully synchronous operation referenced to clock rising edge
· 4-bank operation controlled by BA0,BA1(Bank Address)
· /CAS latency -2/3(programmable,at buffer mode)
· LVTTL Interface
· Burst length 1/2/4/8/Full Page(programmable)
· Burst type- Sequential and interleave burst (programmable)
· Random column access
· Burst Write / Single Write(programmable)
· Auto precharge / All bank precharge controlled by A10
· Auto refresh and Self refresh
· 4096 refresh cycles every 64ms

MH32S72PHB-6 Typical Application

Main memory or graphic memory in computer systems

MH32S72PHB-6 datasheet

MH32S72PHB-6
PDF/DataSheet Download

  • Datasheet: MH32S72PHB-6
  • File Size: 596072 KB
  • Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
  • Click here to Download

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MH32S72PHB-6 Relative Products

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    BANK ACTIVATEThe SDRAM MH32S72PHB -8has four independent banks. Each bank is activated by the ACT command with the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD.T...

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    BANK ACTIVATEThe SDRAM MH32S72PHB -7has four independent banks. Each bank is activated by the ACT command with the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD.T...

  • MH32S72PHB -10

    MH32S72PHB -10

    BANK ACTIVATEThe SDRAM MH32S72PHB -10has four independent banks. Each bank is activated by the ACT command with the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD....

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    The MH32S72DBFA is 33554432 - word x 72-bit Synchronous DRAM stacked structural module. This consist of t hirty-six industry standard 16M x 4 Synchronous DRAMs in TSOP.The stacked structure of TSOP MH32S72DBFAon a card edge dual inline package provides any a...

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