MK50H25

Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the above device. This is a stress rating only and functional operation of the device at these or any other condition above those  ndicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for  xtended periods may affect device reliability.

For added flexibility a transparent mode provides an HDLC transport mechanism without link layer support. This flexible transparent mode may be easily entered and exited without affecting the X.25 link status or the link state variables kept by the MK50H25. In this mode no protocol processing is done and it is up to the user to take care of the upper level software. Single or extended Address field filtering and Control field handling are optionally supported within the transparent mode.

One of the outstanding features of the MK50H25 is its buffer management which includes on-chip dual channel DMA. This feature allows users to receive and transmit multiple data frames at a time. (A conventional serial communications control chip plus a separate DMA chip would handle data for only a single block at a time.) The MK50H25 will move multiple blocks of receive and transmit data directly into and out of memory through the Host's bus. A possible system configuration for the MK50H25 is shown in figure 1.

The MK50H25 may be used with any of several popular 16 and 8 bit microprocessors, such as 68020, 68000, 6800, Z8000, Z80, 8086, 8088, 80186, 80286, 80386SX, etc.

The MK50H25 may be operated in either full or half duplex mode. In half duplex mode, the RTS and CTS modem control pins are provided. In full duplex mode, these pins become user programmable I/O pins. All signal pins on the MK50H25 are TTL compatible. This has the advantage of making the MK50H25 independent of the physical interface. As shown in figure 1, line drivers and receivers are used for electrical connection to the physical layer.