MK74ZD133

The MK74ZD133 is a monolithic CMOS high speed clock driver that includes an on-chip PLL (Phase Locked Loop). Ideal for communications and other systems that require a large number of high-speed clocks, the unique combination of PLL and 32 outputs can eliminate oscillators and multiple low skew buffers. With 32 outputs included in one device, there is also no need to worry about chip-to-chip skew. The zero delay modes cause the input clock rising edge to be synchronized with all of the outputs' rising edges.

The MK74ZD133 has a large selection of built-in multipliers, making it possible to run from a clock input as low as 10 MHz and generate high frequency outputs up to 80 MHz in the SSOP. For speeds up to 133.33 MHz, use the LQFP package.