MK9173-01CS08T General Description
VIDEO GENLOCK PLL
The MK9173-01/-15 provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when using a low frequency input clock to generate a high frequency output clock. The MK9173-01/-15 contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The ICS674-01 can be used as the external feedback divider.
A common application of the MK9173-01/-15 is theimplementation of a video genlock circuit. Because of this, the MK9173-01/-15 inputs operate on the negative-going clock edge.
The MK9173-01/-15 is pin and function compatible to the AV9173-01/15.
The MK9173-01/15 is pin and function compatible to the AV9173-01/15. For new video genlock designs, please refer to the ICS673-01, ICS1522 or ICS1523.
Phase-detector/VCO circuit blockIdeal for genlock systemReference clock range 12 kHz to 1 MHz for full output clock rangeOutput clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See "Allowable Input Frequency to Output Frequency" table for conditionsOn-chip loop filterSingle 5 V power supplyLow power CMOS technology8-pin SOIC packageFor new video genlock applications, please refer to the ICS673-01, ICS1522 or ICS1523.MK9173-01CS08T Maximum Ratings
| Temperature | C |
| Voltage | 3.3 V |
| Package | SOIC 8 |
| Speed | NA |
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