MN85560

• Incorporates the image input filters used for front-end processing.
• Supports PAL size images with just two external 16M synchronous DRAMs (SDRAM).
• The back-end code output buffer is allocated in SDRAM and can be controlled from microcode.
• Provides image quality improvement functions:
• Multiple-mode high-performance motion vector detection
• Original rate control techniques implemented in microcode
• Intra-slice functions for low delay modes and PES output to reduce the system encoding load
• Clock input
• Three clocks: system clock SCLK (27 MHz), video input clock VCLK, and code output clock RCLK.
• An internal PLL circuit is used to generate an 81 MHz clock from SCLK (27 MHz). This clock is used for internal circuits and the synchronous DRAM.
• Supply voltages: 3.3 V (I/O supply voltage and internal PLL circuit supply voltage)
                              1.8 V (internal circuit supply voltage)