Purchase MPC8280, In-stock MPC8280 From SeekIC.
MFG:500 Package Cooled:MOTOROLA D/C:BGA
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MPC8280
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Suppliers
DataSheet
General Description
MPC8280 Maximum Ratings
| Rating |
Symbol |
Value |
Unit |
| Core supply voltage2 |
VDD |
-0.3 2.5 |
V |
| PLL supply voltage2 |
VCCSYN |
-0.3 2.5 |
V |
| I/O supply voltage3 |
VDDH |
-0.3 4.0 |
V |
| Input voltage4 |
VIN |
GND(-0.3) 3.6 |
V |
| Junction temperature |
Tj |
120 |
°C |
| Storage temperature range |
TSTG |
(-55) (+150) |
°C |
not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during
power-on reset
3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec.
VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
MPC8280 Features
The major features of the MPC8280 are as follows:
• Dual-issue integer (G2) core
- A core version of the EC603e microprocessor
- System core microprocessor supporting frequencies of 150450 MHz
- Separate 16-Kbyte data and instruction caches:
Four-way set associative
Physically addressed
LRU replacement algorithm
- PowerPC architecture-compliant memory management unit (MMU)
- Common on-chip processor (COP) test interface
- High-performance (855 Dhrystones MIPS at 450 MHz)
- Supports bus snooping for data cache coherency
- Floating-point unit (FPU)
• Separate power supply for internal logic and for I/O
• Separate PLLs for G2 core and for the CPM
- G2 core and CPM can run at different frequencies for power/performance optimization
- Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios
- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios
• 64-bit data and 32-bit address 60x bus
- Bus supports multiple master designs
- Supports single- and four-beat burst transfers
- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
- Supports data parity or ECC and address parity
• 32-bit data and 18-bit address local bus
- Single-master bus, supports external slaves
- Eight-beat burst transfers
- 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
• 60x-to-PCI bridge
- Programmable host bridge and agent
- 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V
- Synchronous and asynchronous 60x and PCI clock modes
- All internal address space available to external PCI host
- DMA for memory block transfers
- PCI-to-60x address remapping
• PCI bridge
- PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
- On-chip arbitration
- Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming
- PCI Host Bridge or Peripheral capabilities
- Includes 4 DMA channels for the following transfers:
PCI-to-60x to 60x-to-PCI
60x-to-PCI to PCI-to-60x
PCI-to-60x to PCI-to-60x
60x-to-PCI to 60x-to-PCI
- Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8280) required by the PCI standard as well as message and doorbell registers
- Supports the I2O standard
- Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998)
- Support for 66.67/83.33/100 MHz, 3.3 V specification
- 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
- Makes use of the local bus signals, so there is no need for additional pins
• System interface unit (SIU)
- Clock synthesizer
- Reset controller
- Real-time clock (RTC) register
- Periodic interrupt timer
- Hardware bus monitor and software watchdog timer
- IEEE 1149.1 JTAG test access port
• Twelve-bank memory controller
- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals
- Byte write enables and selectable parity generation
- 32-bit address decodes with programmable bank size
- Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine
- Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
- Dedicated interface logic for SDRAM
• CPU core can be disabled and the device can be used in slave mode to an external core
• Communications processor module (CPM)
- Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols
- Interfaces to G2 core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-Kbyte dual-port instruction RAM and DMA controller
- Serial DMA channels for receive and transmit on all serial channels
- Parallel I/O registers with open-drain and interrupt capability
- Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
- Three fast communications controllers supporting the following protocols:
10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) or reduced media independent interface (RMII)
ATM-Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections (no ATM support for the MPC8270)
Transparent
HDLC-Up to T3 rates (clear channel)
FCC2 can also be connected to the TC layer (MPC8280 only)
- Two multichannel controllers (MCCs) (one MCC on the MPC8270)
Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each.
Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC
- Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols:
Ethernet/IEEE 802.3 CDMA/CS
HDLC/SDLC and HDLC bus
Universal asynchronous receiver transmitter (UART)
Synchronous UART
Binary synchronous (BISYNC) communications
Transparent
- Universal serial bus (USB) controller-supports both host and slave modes
- Two serial management controllers (SMCs), identical to those of the MPC860
Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision- multiplexed (TDM) channels
Transparent
UART (low-speed operation)
- One serial peripheral interface identical to the MPC860 SPI
- One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller)
Microwire compatible
Multiple-master, single-master, and slave modes
- Up to eight TDM interfaces (four on the MPC8270)
Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8270)
2,048 bytes of SI RAM
Bit or byte resolution
Independent transmit and receive routing, frame synchronization
Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces
- Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels
- Four independent 16-bit timers that can be interconnected as two 32-bit timers
• Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only).Supported by eight transfer transmission convergence (TC) layers between the TDMs and FCC2.
• Transmission convergence (TC) layer (MPC8280 only)
• Dual-issue integer (G2) core
- A core version of the EC603e microprocessor
- System core microprocessor supporting frequencies of 150450 MHz
- Separate 16-Kbyte data and instruction caches:
Four-way set associative
Physically addressed
LRU replacement algorithm
- PowerPC architecture-compliant memory management unit (MMU)
- Common on-chip processor (COP) test interface
- High-performance (855 Dhrystones MIPS at 450 MHz)
- Supports bus snooping for data cache coherency
- Floating-point unit (FPU)
• Separate power supply for internal logic and for I/O
• Separate PLLs for G2 core and for the CPM
- G2 core and CPM can run at different frequencies for power/performance optimization
- Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios
- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios
• 64-bit data and 32-bit address 60x bus
- Bus supports multiple master designs
- Supports single- and four-beat burst transfers
- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
- Supports data parity or ECC and address parity
• 32-bit data and 18-bit address local bus
- Single-master bus, supports external slaves
- Eight-beat burst transfers
- 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
• 60x-to-PCI bridge
- Programmable host bridge and agent
- 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V
- Synchronous and asynchronous 60x and PCI clock modes
- All internal address space available to external PCI host
- DMA for memory block transfers
- PCI-to-60x address remapping
• PCI bridge
- PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
- On-chip arbitration
- Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming
- PCI Host Bridge or Peripheral capabilities
- Includes 4 DMA channels for the following transfers:
PCI-to-60x to 60x-to-PCI
60x-to-PCI to PCI-to-60x
PCI-to-60x to PCI-to-60x
60x-to-PCI to 60x-to-PCI
- Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8280) required by the PCI standard as well as message and doorbell registers
- Supports the I2O standard
- Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998)
- Support for 66.67/83.33/100 MHz, 3.3 V specification
- 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
- Makes use of the local bus signals, so there is no need for additional pins
• System interface unit (SIU)
- Clock synthesizer
- Reset controller
- Real-time clock (RTC) register
- Periodic interrupt timer
- Hardware bus monitor and software watchdog timer
- IEEE 1149.1 JTAG test access port
• Twelve-bank memory controller
- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals
- Byte write enables and selectable parity generation
- 32-bit address decodes with programmable bank size
- Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine
- Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
- Dedicated interface logic for SDRAM
• CPU core can be disabled and the device can be used in slave mode to an external core
• Communications processor module (CPM)
- Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols
- Interfaces to G2 core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-Kbyte dual-port instruction RAM and DMA controller
- Serial DMA channels for receive and transmit on all serial channels
- Parallel I/O registers with open-drain and interrupt capability
- Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
- Three fast communications controllers supporting the following protocols:
10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) or reduced media independent interface (RMII)
ATM-Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections (no ATM support for the MPC8270)
Transparent
HDLC-Up to T3 rates (clear channel)
FCC2 can also be connected to the TC layer (MPC8280 only)
- Two multichannel controllers (MCCs) (one MCC on the MPC8270)
Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each.
Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC
- Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols:
Ethernet/IEEE 802.3 CDMA/CS
HDLC/SDLC and HDLC bus
Universal asynchronous receiver transmitter (UART)
Synchronous UART
Binary synchronous (BISYNC) communications
Transparent
- Universal serial bus (USB) controller-supports both host and slave modes
- Two serial management controllers (SMCs), identical to those of the MPC860
Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision- multiplexed (TDM) channels
Transparent
UART (low-speed operation)
- One serial peripheral interface identical to the MPC860 SPI
- One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller)
Microwire compatible
Multiple-master, single-master, and slave modes
- Up to eight TDM interfaces (four on the MPC8270)
Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8270)
2,048 bytes of SI RAM
Bit or byte resolution
Independent transmit and receive routing, frame synchronization
Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces
- Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels
- Four independent 16-bit timers that can be interconnected as two 32-bit timers
• Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only).Supported by eight transfer transmission convergence (TC) layers between the TDMs and FCC2.
• Transmission convergence (TC) layer (MPC8280 only)
MPC8280ED
PDF/DataSheet Download
- Datasheet: MPC8280ED
- File Size: 1232127 KB
- Manufacturer: Motorola
- Click here to Download
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