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MFG:11000  Package Cooled:OKI  

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Part Number: MSM5718C50

 

MFG: 11000

Package Cooled: OKI

 

Description: The 18/64-Megabit Concurrent Rambus™ DRAMs (RDRAM®) are extremely high-speed CMOS DRAMs orga...


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MSM5718C50 General Description


The 18/64-Megabit Concurrent Rambus™ DRAMs (RDRAM®) are extremely high-speed CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits. They are capable of bursting unlimited lengths of data at 1.67 ns per byte (13.3 ns per eight bytes). The use of Rambus Signaling Level (RSL) technology permits 600 MHz transfer rates while using conventional system and board design methodologies. Low effective latency is attained by operating the two or four 2KB sense amplifiers as high speed caches, and by using random access mode (page mode) to facilitate large block transfers. Concurrent (simultaneous) bank operations permit high effective bandwidth using interleaved transactions.

RDRAMs are general purpose high-performance memory devices suitable for use in a broad range of applications including PC and consumer main memory, graphics, video, and any other application where high-performance at low cost is required.

MSM5718C50 Maximum Ratings

Symbol
Parameter
Min.
Max.
Unit
V I,ABS
Voltage applied to any RSL pin with respect to Gnd
0.3
V DD,MAX+0.3
V
V I,CMOS,ABS
Voltage applied to any CMOS pin with respect to Gnd
0.3
V DD+0.3
V
V DD,ABS
Voltage on VDD with respect to Gnd
0.3
VDD,MAX+1.0
V
T J,ABS
Junction temperature under bias
55
125
°C
T STORE
Storage temperature
55
125
°C

MSM5718C50 Features

• Compatible with Base RDRAMs
• 600 MB/s peak transfer rate per RDRAM
• Rambus Signaling Level (RSL) interface
• Synchronous, concurrent protocol for block-oriented, interleaved (overlapped) transfers
• 480 MB/s effective bandwidth for random 32 byte transfers from one RDRAM
• 13 active signals require just 32 total pins on the controller interface (including power)
• 3.3 V operation
• Additional/multiple Rambus Channels each provide an additional 600 MB/s bandwidth
• Two or four 2KByte sense amplifiers may be operated as caches for low latency access
• Random access mode enables any burst order at full bandwidth within a page
• Graphics features include write-per-bit and mask-per-bit operations
• Available in horizontal surface mount plastic package (SHP32-P-1125-0.65-K)

MSM5718C50 Connection Diagram

MSM5718C50  Connection Diagram

MSM5718C50 datasheet

MSM5718C50
PDF/DataSheet Download

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