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Part Number: MT28C3214P2NFL
Description: The MT28C3214P2FL and MT28C3214P2NFL combination Flash and SRAM memory devices provide a compact, low-...
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MT28C3214P2NFL
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General Description
MT28C3214P2NFL General Description
The MT28C3214P2FL and MT28C3214P2NFL combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash is a high-performance, high-density, nonvolatile memory device with a revolutionary architecture that can significantly improve system performance.
This new architecture features:
• A two-memory-bank configuration supporting
dual-bank burst operation;
• A high-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The device also provides soft protection for blocks by configuring soft protection registers with dedicated command sequences. For security purposes, dual 64- bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register, one for each bank, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command.
The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages.
The device takes advantage of a dedicated power source for the Flash device (F_VCC) and a dedicated power source for the SRAM device (S_VCC), both at 1.65V1.95V or 1.80V2.20V for optimized power consumption and improved noise immunity. The MT28C3214P2FL and MT28C3214P2NFL devices support two VPP voltage ranges, VPP1 and VPP2. VPP1 is an in-circuit voltage of 0.9V2.2V (MT28C3214P2FL) or 0.0V2.2V (MT28C3214P2NFL). VPP2 is the production compatibility voltage of 12V ±5%. The 12V ±5% VPP2 is supported for a maximum of 100 cycles and 10 cumulative hours. See Table 1.
The MT28C3214P2FL and MT28C3214P2NFL devices contain an asynchronous 4Mb SRAM organized as 256K-words by 16 bits. These devices are fabricated using an advanced CMOS process and high-speed/ ultra-low-power circuit technology.
The MT28C3214P2FL and MT28C3214P2NFL devices are packaged in a 66-ball FBGA package with 0.80mm pitch.
MT28C3214P2NFL Maximum Ratings
Voltage to Any Pin Except VCC and VPP
with Respect to VSS ............................ -0.5V to +2.45V
VPP Voltage (for BLOCK ERASE and PROGRAM
with Respect to VSS) ....................... -0.5V to +13.5V**
VCC and VCCQ Supply Voltage
with Respect to VSS ............................ -0.3V to +2.45V
Output Short Circuit Current.............................. 100mA
Operating Temperature Range ............ -40 to +85
Storage Temperature Range ............. -55 to +125
Soldering Cycle ...................................... 260 for 10s
with Respect to VSS ............................ -0.5V to +2.45V
VPP Voltage (for BLOCK ERASE and PROGRAM
with Respect to VSS) ....................... -0.5V to +13.5V**
VCC and VCCQ Supply Voltage
with Respect to VSS ............................ -0.3V to +2.45V
Output Short Circuit Current.............................. 100mA
Operating Temperature Range ............ -40 to +85
Storage Temperature Range ............. -55 to +125
Soldering Cycle ...................................... 260 for 10s
MT28C3214P2NFL Features
• Flexible dual-bank architecture
• Support for true concurrent operations with no
latency:
Read bank b during program bank a and vice versa
Read bank b during erase bank a and vice versa
• Organization: 2,048K x 16 (Flash)
256K x 16 (SRAM)
• Basic configuration:
Flash
Bank a (4Mb Flash for data storage)
Eight 4K-word parameter blocks
Seven 32K-word blocks
Bank b (28Mb Flash for program storage)
Fifty-six 32K-word main blocks
SRAM
4Mb SRAM for data storage
256K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages1
1.65V (MIN)/1.95V (MAX) F_VCC read voltage or
1.80V (MIN)/2.20V (MAX) F_VCC read voltage
1.65V (MIN)/1.95V (MAX) S_VCC read voltage or
1.80V (MIN)/2.20V (MAX) S_VCC read voltage
1.65V (MIN)/1.95V (MAX) VCCQ or
1.80V (MIN)/2.20V (MAX) VCCQ
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
0.0V (MIN)/2.20V (MAX) F_VPP (in-system
PROGRAM/ERASE)2
12V ±5% (HV) F_VPP (production programming
compatibility)
• Asynchronous access time1
Flash access time: 100ns or 110ns @ 1.65V F_VCC
SRAM access time: 100ns @ 1.65V S_VCC
• Page Mode read access1
Interpage read access: 100ns/110ns @ 1.65V F_VCC
Intrapage read access: 35ns/45ns @ 1.65V F_VCC
• Low power consumption
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
purposes
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
Extended command set
Common flash interface (CFI) compliant
MT28C3214P2NFL
PDF/DataSheet Download
- Datasheet: MT28C3214P2NFL
- File Size: 532625 KB
- Manufacturer: MICRON [Micron Technology]
- Click here to Download
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