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Part Number: MT28F004B5-1

 

 

 

 

Description: The MT28F004B5 (x8) and MT28F400B5 (x16, x8) are nonvolatile, electrically block-erasable (Flash), pro...


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MT28F004B5-1 General Description


The MT28F004B5 (x8) and MT28F400B5 (x16, x8) are nonvolatile, electrically block-erasable (Flash), programmable, read-only memories containing 4,194,304 bits organized as 262,144 words (16 bits) or 524,288 bytes (8 bits). Writing or erasing the device is done with a 5V VPP voltage, while all operations are performed with a 5V VCC. Due to process technology advances, 5V VPP is optimal for application and production programming. These devices are fabricated with Micron's advanced 0.18m CMOS floating-gate process.

The MT28F004B5 and MT28F400B5 are organized into seven separately erasable blocks. To ensure that critical firmware is protected from accidental erasure or overwrite, the devices feature a hardware-protected boot block. Writing or erasing the boot block requires either applying a super-voltage to the RP# pin or driving WP# HIGH in addition to executing the normal write or erase sequences. This block may be used to store code implemented in low-level system recovery. The remaining blocks vary in density and are written and erased with no additional security measures.

MT28F004B5-1 Maximum Ratings

Voltage on VCC Supply Relative to VSS ....-0.5V to +6V**
Input Voltage Relative to VSS ..................-0.5V to +6V**
VPP Voltage Relative to VSS.................... -0.5V to +5.5V†
RP# or A9 Pin Voltage
Relative to Vss ...................................   -0.5V to +12.6V†
Temperature Under Bias..........................-40ºC to +85ºC
Storage Temperature (plastic) ..............-55ºC to +125ºC
Power Dissipation .......................................................1W

MT28F004B5-1 Features

• Seven erase blocks:
   16KB/8K-word boot block (protected)
   Two 8KB/4K-word parameter blocks
   Four main memory blocks
• Smart 5 technology (B5):
   5V ±10% VCC
   5V ±10% VPP application/production
   programming1
• Advanced 0.18m CMOS floating-gate process
• Compatible with 0.3m Smart 5 device
• Address access time: 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
   (MT28F400B5, 256K x 16/512K x 8)
• Byte-wide READ and WRITE only
   (MT28F004B5, 512K x 8)
• TSOP and SOP packaging options

MT28F004B5-1 datasheet

MT28F004B5-1
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