MT48LC16M16A2

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4's 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8's 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16's 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used PART NUMBER ARCHITECTURE PACKAGE MT48LC64M4A2TG 64 Meg x 4 54-pin TSOP II MT48LC64M4A2FB* 64 Meg x 4 60-ball FBGA MT48LC32M8A2TG 32 Meg x 8 54-pin TSOP II MT48LC32M8A2FB* 32 Meg x 8 60-ball FBGA MT48LC16M16A2TG 16 Meg x 16 54-pin TSOP II MT48LC16M16A2FG 16 Meg x 16 54-ball FBGA *Actual FBGA part marking shown on page 58. 256 Mb SDRAM PART NUMBERS to select the bank and row to be accessed (BA0, BA1 select the bank; A0A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, random-access operation.

The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.