MT48LC16M16A2P-75IT

The MT48LC16M16A2P-75IT is one member of the MT48LC16M16 family which is designed as the high-speed CMOS, dynamic random-access memory device that has some points of features:(1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal, pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto precharge, includes concurrent auto precharge and auto refresh modes; (7)Self refresh mode (not available on AT devices); (8)Auto refresh: 64ms, 8192-cycle (commercial and industrial) and 16ms, 8192-cycle (automotive); (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ?.3V power supply.

This MT48LC16M16A2P-75IT is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK), and provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option.

The absolute maximum ratings of the MT48LC16M16A2P-75IT can be summarized as:(1)Voltage on VDD/VDDQ supply relative to VSS: -1 to 4.6 V;(2)Voltage on inputs, NC, or I/O balls relative to VSS: -1 to 4.6 V;(3)Storage temperature (plastic): 55 to +150 °C;(4)Power dissipation: 1 W. If you want to know more information such as the electrical characteristics about MT48LC16M16A2P-75IT, please download the datasheet in www.seekic.com or www.chinaicmart.com.