MT48LC4M32B2P-6

The MT48LC4M32B2P-6 is designed as one kind of high-speed CMOS, dynamic random-access memory which containing 134,217,728 bits. MT48LC4M32B2P-6 is internally configured as a quad-bank DRAM with a synchronous interface.It uses an internal pipelined architecture to achieve high-speed operation.This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access.

Features of the MT48LC4M32B2P-6 are:(1)PC100-compliant;includes concurrent auto precharge;(2)fully synchronous, all signals registered on positive edge of system clock;(3)internal pipelined operation, column address can be changed every clock cycle;(4)internal banks for hiding row access / precharge;(5)programmable burst lengths:1,2,4,8 or full page;(6)auto precharge and auto refresh modes;(7)self refresh mode;(8)64 ms, 4,096-cycle refresh;(9)single +3.3V+/-0.3V power supply;(10)one and two clock write recovery versions.

The absolute maximum ratings of the MT48LC4M32B2P-6 can be summarized as:(1)operating temperature,Ta (ambient):-1V to +4.6V;(2)storage tempera-ture (plastic):-55 to +150;(3)power dissipation:1 W.If you want to know more information such as the electrical characteristics about MT48LC4M32B2P-6, please download the datasheet in www.seekic.com or www.chinaicmart.com .