MT48LC8M32B2P-6

The MT48LC8M32B2P-6 is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits.It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits.The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided,along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.

It has many unique features: (1) PC100 functionality; (2) fully synchronous; all signals registered on positive edge of system clock; (3) internal pipelined operation; column address can be changed every clock cycle; (4) internal banks for hiding row access/precharge; (5) programmable burst lengths are 1, 2, 4, 8, or full page; (6) self refresh mode; (7) 64ms, 4,096-cycle refresh (15.6s/row); (8) single +3.3V ±0.3V power supply.

There are some absolute maximum ratings about it. (1): voltage on VDD, VDDQ supply relative to VSS is -1V to +4.6V; (2): voltage on inputs, NC or I/O Pins relative to VSS is -1V to +4.6V; (3): operating temperature(Ta) is 0°C to +70°C; (4): storage temperature (plastic) is -55°C to +150°C; (5): power dissipation is 1W.