MT49H16M16

Features:

• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Cyclic bank addressing for maximum data out bandwidth
• Non-multiplexed addresses
• Non-interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR
• Target 600 Mb/s/p data rate
• Programmable Read Latency (RL) of 5-8
• Data valid signal (DVLD) activated as read data is available
• Data Mask signals (DM0/DM1) to mask first and second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• Pseudo-HSTL 1.8V I/O Supply
• Internal Auto Precharge
• Refresh requirements: 32ms at 100°C junction temperature (8K refresh for each bank, 64K refresh command must be issued in total each 32ms)


Specifications

Storage Temperature .............................-55°C to +150°C
I/O Voltage ................................. -0.3V to + VDDQ + 0.3V
Voltage on VEXT Supply Relative to VSS ... -0.3V to +2.8V
Voltage on VDD Supply Relative to VSS ..... -0.3V to +2.1V
Voltage on VDDQ Supply Relative to VSS .. -0.3V to +2.1V
Junction Temperature** .........................................100°C


Description

The Micron 256Mb MT49H16M16 Reduced Latency DRAM RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format where the data is provided and synchronized with differential echo clock signal. RLDRAM MT49H16M16 does not requirerow/column address multiplexing and is optimized for fast random access and high-speed bandwidth.

RLDRAM MT49H16M16 is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.