MT49H16M18

Features: • 400 MHz DDR operation (800 Mb/s/pin data rate)• Organization 8 Meg x 36, 16 Meg x 18, and 32 Meg x 9 8 banks• Cyclic bank switching for maximum bandwidth• Reduced cycle time (20ns at 400 MHz)• Nonmultiplexed addresses (address multiplexing option available...

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SeekIC No. : 004429871 Detail

MT49H16M18: Features: • 400 MHz DDR operation (800 Mb/s/pin data rate)• Organization 8 Meg x 36, 16 Meg x 18, and 32 Meg x 9 8 banks• Cyclic bank switching for maximum bandwidth• Reduced...

floor Price/Ceiling Price

Part Number:
MT49H16M18
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

• 400 MHz DDR operation (800 Mb/s/pin data rate)
• Organization 8 Meg x 36, 16 Meg x 18, and 32 Meg x 9 8 banks
• Cyclic bank switching for maximum bandwidth
• Reduced cycle time (20ns at 400 MHz)
• Nonmultiplexed addresses (address multiplexing option available)
• SRAM-type interface
• Programmable READ latency (RL), row cycle time, and burst sequence length
• Balanced READ and WRITE latencies in order to optimize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-chip DLL generates CK edge-aligned data and output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms)
• 144-ball BGA package
• HSTL I/O (1.5V or 1.8V nominal)
• 2560 matched impedance outputs
• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
• On-die termination (ODT) RTT



Specifications

Parameter
Min
Max
Units
Notes
Storage temperature
-55
+150
°C
I/O voltage
-0.3V
VDDQ + 0.3
V
Voltage on VEXT supply relative to VSS
-0.3
+2.8
V
Voltage on VDD supply relative to VSS
-0.3
+2.1
V
Voltage on VDDQ supply relative to VSS
-0.3
+2.1
V
Junction temperature
110
°C
1
Notes: 1. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.


Description

The Micron® 288Mb reduced latency DRAM (RLDRAM®) II MT49H16M18 is a high-speed memory device designed for high bandwidth communication data storage-telecommunications, networking, and cache applications, etc. The MT49H16M18's 8-bank architecture is optimized for high speed and achieves a peak bandwidth of 28.8 Gb/s, using a 36-bit interface and a maximum system clock of 400 MHz.

The double data rate (DDR) interface of MT49H16M18 transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the I/O pins. Output data is referenced to the free-running output data clock.

Commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data clock(s).

Read and write accesses to the RLDRAM MT49H16M18 are burst-oriented. The burst length is programmable from 2, 4, or 81 by setting the mode register.

The MT49H16M18 is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers.

Bank-scheduled refresh of MT49H16M18 is supported with row address generated internally. A standard BGA 144-ball package is used to enable ultra high-speed data transfer rates and a simple upgrade path from former products.
Notes: 1. Burst of 8 on x18 and x9 devices only.




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