MT5C 1008

The MT5C1008 SRAM MT5C 1008 employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology.

For design flexibility in high-speed memory applications, this MT5C 1008 offers dual chip enables (CE1\, CE2) and output enable (OE\). These control pins can place the outputs in High-Z for additional flexibility in system design. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible.

Writing to these MT5C 1008 is accomplished when write enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH. Reading is accomplished when WE\ and CE2 remain HIGH and CE1\ and OE\ go LOW. The MT5C 1008 offer a reduced power standby mode when disabled, allowing system designs to achieve low standby power requirements.

The "L" version offers a 2V data retention mode, reducing current consumption to 1mA maximum.