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Part Number: MT9074AP
Description: The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T...
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MT9074AP
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DataSheet
General Description
MT9074AP General Description
The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T1 (T1 mode) or PCM 30 (E1 mode) framer with a Line Interface Unit (LIU).
The framer interfaces to a 2.048 Mbit/s backplane providing selectable data link access with optional HDLC controllers for either the FDL bits and channel 24 (T1 mode) or Sa bits and channel 16 (E1 mode). The LIU interfaces the framer to T1 (T1 mode) or PCM 30 (E1 mode) transformer-isolated four-wire line with minimal external components required.
In T1 mode the MT9074 supports D4, ESF and SLC- 96 formats, meeting the latest recommendations including ITU I.431, AT&T PUB43801, TR-62411, ANSI T1.102, T1.403 and T1.408. In E1 mode the MT9074 supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM 30, and I.431 for ISDN primary rate. It also supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233.
MT9074AP Maximum Ratings
| Parameter | Symbol | Min. | Max. | Units | |
| 1 | Supply Voltage | VDD | -0.3 | 7 | V |
| 2 | Voltage at Digital Inputs | VI | -0.3 | VDD+0.3 | V |
| 3 | Current at Digital Inputs | VI | 30 | mA | |
| 4 | Voltage at Digital Outputs | VO | -0.3 | VDD+0.3 | V |
| 5 | Current at Digital Outputs | IO | 30 | mA | |
| 6 | Storage Temperature | TST | -65 | 150 |
MT9074AP Features
• Combined E1 (PCM 30) and T1 (D4/ESF) framer, Line Interface Unit (LIU) and link controller with optional digital framer only mode
• In T1 mode the LIU can recover signals attenuated by up to 36 dB (6000 ft. of 24 AWG cable)
• In E1 mode the LIU can recover signals attenuated by up to 36 dB (2000 m. of 0.65mm cable)
• Two HDLCs: FDL and channel 24 in T1 mode, timeslot 0 (Sa bits) and timeslot 16 in E1 mode
• Two-frame elastic buffer in Rx & Tx (T1) directions
• Programmable transmit delay through transmit slip buffer
• Low jitter DPLL for clock generation
• Enhanced alarms, performance monitoring and error insertion functions
• Intel or Motorola non-multiplexed parallel microprocessor interface
• ST-BUS 2.048 Mbit/s backplane bus for both data and signaling
• Japan Telecom J1 Framing and Yellow Alarm
• Hardware data link access
• JTAG Boundary Scan
• In T1 mode the LIU can recover signals attenuated by up to 36 dB (6000 ft. of 24 AWG cable)
• In E1 mode the LIU can recover signals attenuated by up to 36 dB (2000 m. of 0.65mm cable)
• Two HDLCs: FDL and channel 24 in T1 mode, timeslot 0 (Sa bits) and timeslot 16 in E1 mode
• Two-frame elastic buffer in Rx & Tx (T1) directions
• Programmable transmit delay through transmit slip buffer
• Low jitter DPLL for clock generation
• Enhanced alarms, performance monitoring and error insertion functions
• Intel or Motorola non-multiplexed parallel microprocessor interface
• ST-BUS 2.048 Mbit/s backplane bus for both data and signaling
• Japan Telecom J1 Framing and Yellow Alarm
• Hardware data link access
• JTAG Boundary Scan
MT9074AP Typical Application
• E1/T1 add/drop multiplexers and channel banks
• CO and PBX equipment interfaces
• Primary Rate ISDN nodes
• Digital Cross-connect Systems (DCS)
• CO and PBX equipment interfaces
• Primary Rate ISDN nodes
• Digital Cross-connect Systems (DCS)
MT9074AP Connection Diagram
MT9074AP
PDF/DataSheet Download
- Datasheet: MT9074AP
- File Size: 381691 KB
- Manufacturer: MITEL [Mitel Networks Corporation]
- Click here to Download
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