Purchase MX29F001T, In-stock MX29F001T From SeekIC.
Part Number: MX29F001T
Description: The MX29F001T/B is a 1-mega bit Flash memory organized as 128K bytes of 8 bits only MXIC's Flash memor...
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MX29F001T
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General Description
MX29F001T General Description
The MX29F001T/B is a 1-mega bit Flash memory organized as 128K bytes of 8 bits only MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F001T/B is packaged in 32-pin PLCC, TSOP, PDIP. It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers.
The standard MX29F001T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F001T/B has separate chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F001T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F001T/B uses a 5.0V ± 10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
MX29F001T Maximum Ratings
|
RATING |
VALUE |
|
Ambient Operating Temperature |
0oC to 70oC |
|
Storage Temperature |
-65oC to 125oC |
|
Applied Input Voltage |
0.5V to 7.0V |
|
Applied Output Voltage |
0.5V to 7.0V |
|
VCC to Ground Potential |
0.5V to 7.0V |
|
A9&OE |
-0.5V to 13.5V |
MX29F001T Features
• 5.0V ± 10% for read, erase and write operation
• 131072x8 only organization
• Fast access time: 55/70/90/120ns
• Low power consumption
30mA maximum active current(5MHz)
1uA typical standby current
• Command register architecture
Byte Programming (7us typical)
Sector Erase (8K-Byte x1,4K-Byte x 2, 8K Bytex2, 32K-Bytex1, and 64K-Byte x1)
• Auto Erase (chip & sector) and Auto Program
Automatically erase any combination of sectors with Erase Suspend capability.
Automatically programs and verifies data at speci fied address
• Erase Suspend/Erase Resume
Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation.
• Status Reply
Data polling & Toggle bit for detection of program and erase cycle completion.
• Chip protect/unprotect for 5V only system or 5V/12V system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
T = Top Boot Sector
B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
32-pin PLCC
32-pin TSOP
32-pin PDIP
• Boot Code Sector Architecture
T=Top Boot Sector
B=Bottom Boot Sector
• 20 years data retention
• 131072x8 only organization
• Fast access time: 55/70/90/120ns
• Low power consumption
30mA maximum active current(5MHz)
1uA typical standby current
• Command register architecture
Byte Programming (7us typical)
Sector Erase (8K-Byte x1,4K-Byte x 2, 8K Bytex2, 32K-Bytex1, and 64K-Byte x1)
• Auto Erase (chip & sector) and Auto Program
Automatically erase any combination of sectors with Erase Suspend capability.
Automatically programs and verifies data at speci fied address
• Erase Suspend/Erase Resume
Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation.
• Status Reply
Data polling & Toggle bit for detection of program and erase cycle completion.
• Chip protect/unprotect for 5V only system or 5V/12V system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
T = Top Boot Sector
B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
32-pin PLCC
32-pin TSOP
32-pin PDIP
• Boot Code Sector Architecture
T=Top Boot Sector
B=Bottom Boot Sector
• 20 years data retention
MX29F001T Connection Diagram
MX29F001T
PDF/DataSheet Download
- Datasheet: MX29F001T
- File Size: 897429 KB
- Manufacturer: MCNIX [Macronix International]
- Click here to Download
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