MX805A

• Non-predictive CTCSS Tone Decoder
• DCS Sub-Audio Signal demodulator
• CTCSS /NRZ Encoder with TX level adjustment and lowpass filter output stage with optional NRZ pre-emphasis
• Selectable Sub-Audio bandstop filter
• NoTone (CTCSS RX) period timer
• Low Power Operation
• Member of DBS800 Family (C-BUS Compatible)

The MX805A is a sub-audio frequency signaling processor that provides outband audio and digital signaling capability for LMR systems. Designed for the transmission and non-predictive reception of Continuous Tone Controlled Squelch (CTCSS) tones and other non-standard frequencies, the MX805A also handles Non- Return-to Zero (NRZ) data reception and transmission to provide Digitally Coded Squelch (DCS/DPLTM) and LTRTM signaling.

Setting the MX805A functions and modes is accomplished by data loaded from the microcontroller to the controlling registers within the device. Reply Data and Interrupt protocol keep the microcontroller up to date on the operational status of the circuitry. CTCSS tone data for transmission is generated in the microcontroller, loaded to the CTCSS TX Frequency Register, encoded and output as a tone via the TX Subaudio LPF. Received non-predicted CTCSS tone frequencies are measured and the resulting data, in the form of a 2-byte data word, is presented to the microcontroller for matching against a lookup table. Noise filtering is provided to improve the signal quality prior to measurement. NRZ coded data streams for transmission, when generated within a microcontroller, are loaded to the NRZ TX Data Buffer and output, in 8-bit bytes, through the lowpass filter circuitry as subaudible signals. DCS turnoff tones can be added to the data signals by switching the MX805A to the CTCSS transmit mode at the appropriate time. NRZ coding is produced by the microcontroller and translated to subaudio signals by the MX805A. Received NRZ data is filtered, detected, and placed into the NRZ Data Register, which is then available for transfer (one byte at a time) to the microcontroller for decoding by software. Clock extraction circuitry is provided on-chip. TX ad RX baud rates are selectable.

Hardware and software are designed to allow consecutive addressing of two MX805A Sub-Audio Signaling Processors to achieve multi-mode duplex operation. Powersaving may be controlled by software or by an input dedicated to the purpose.

The MX805A may be used with a 5.0V power supply and is available in the following packages: 24-pin SOIC (MX805ADW), 24-pin PLCC (MX805ALH), and 24-pin PDIP (MX805AP).