MX93000C General Description
. Clock Rate (REG4 bit(2))
. The clock rate (MCLK) must be set before using functionality of the MX93000C
. Programmable clock rate :
1. 2.048MHz (Frame Sync. 8KHz)
2. 1.536MHz (Frame Sync. 8KHz)
. Data Format (REG4 bit(1,0))
. The data format must be set before using functionality of the MX93000C
. Programmable Data Format
1. 16-bit linear data format (it can get 14-bit resolution and higher linearity than that of u/a-law data format)
2. 8-bit u-law data format
3. 8-bit a-law data format
MX93000C Features
. Single +5V power supply PCM CODEC
. Support.../A law and 16-bit format linear data
. Support switch paths for DAM (digital answering machine) related product application
. Support power-low and battery-low detectors
. Support power on reset function for DSP and MCU use
. Support external L.P.F for D/A output path
. Support external volume control
. On-chip differential line driver
. On-chip ALC (automatic level control)
. On-chip digital volume control
. On-chip programmable receive/transmit gain control
. Easy interface to general purpose DSP
. Easy Read/Write of control registers by MCU
. Easy interface to FAX or Cordless phone
. Automatic power-down function
. Support 2.048 or 1.536MHz master clock
. Support smart power management
. 28-pin SOP/DIP package
MX93000C Connection Diagram
Map list: ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789All