NLAS4053

Features:

• Improved RDS(on) Specifications
• Pin for Pin Replacement for MAX4053 and MAX4053A
   One Half the Resistance Operating at 5.0 Volts
• Single or Dual Supply Operation
   Single 35 Volt Operation, or Dual ±3 Volt Operation
   With V_CC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
   No Translators Needed
   Address and Inhibit Pins are OverVoltage Tolerant and May Be
   Driven Up +6 V Regardless of V_CC
• Address and Control Pins are Standard TTL Compatible
   Greatly Improved Noise Margin Over MAX4053 and MAX4053A
• Improved Linearity Over Standard HC4053 Devices
• Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin Packages


Pinout




Specifications

Symbol	Parameter	Value	Unit
VEE	Negative DC Supply Voltage (Referenced to GND)	-0.7 to + 0.5
VCC	DC Supply Voltage	-0.5 to +7.0 -0.5 to +7.0	V
VI	DC Input Voltage	VEE-0.5 to + 0.5	V
VO	DC Output Voltage Output in Higher or Low State (Note 1)	-0.5 Vis + 0.5	V
IIK	DC Input Diode Current VI < GND	-50	mA
IOK	DC Output Diode Current VO = GND VO = VCC	-50	mA
IOU	DC Output Sink Current	±50	mA
ICC	DC Supply Current per Supply Pin	±100	mA
IGND	DC Ground Current per Ground Pin	±100	mA
TSTG	Storage Temperature Range	-65 to +150	°C
TL	Lead Temperature, 1 mm from Case for 10 Seconds	260	°C
TJ	Junction Temperature Under Bias	+150	°C
JA	Thermal Resistance SOT- 353 (Note 1) SOT- 553	500 450 450	°C/W
PD	Power Dissipation in Still Air at 85°C	500 450 450	mW
MSL	Moisture Sensitivity	Level 1
FR	Flammability Rating Oxygen Index: 28 to 34	UL 94 V0 @ 0.125 in
VESD	ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4)	> 2000 200 N/A	V
ILatchUp	LatchUp Performance Above VCC and Below GND at 85°C(Note 5)	±300	mA

1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximumrated conditions is not implied.
2. The absolute value of VCC± |V_EE| 3 7.0.
3. Tested to EIA/JESD22A114A.
4. Tested to EIA/JESD22A115A.
5. Tested to JESD22C101A.
6. Tested to EIA/JESD78.

Description

The NLAS4053 is an improved version of the MC14053 and MC74HC4053 fabricated in submicron Silicon Gate CMOS technology for lower RDS(on) resistance and improved linearity with low current. NLAS4053 may be operated either with a single supply or dual supply up to ±3 V to pass a 6 VPP signal without coupling capacitors.

When operating in single supply mode, NLAS4053 is only necessary to tie V_EE, pin 7 to ground. For dual supply operation, V_EE is tied to a negative voltage, not to exceed maximum ratings. Pin for pin compatible with all industry standard versions of '4053.'