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MFG:ON  Package Cooled:QFN16  D/C:2005  

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Part Number: NLSF3T125

 

MFG: ON

Package Cooled: QFN16

D/C: 2005

Description: The NLSF3T125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It ac...


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NLSF3T125 General Description


The NLSF3T125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The NLSF3T125 requires the 3?state control input (OE) to be set High to place the output into the high impedance state.

The T125 inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings.

The NLSF3T125 input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage  input/output voltage mismatch, battery backup, hot insertion, etc.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.

NLSF3T125 Maximum Ratings

Symbol Parameter Value Unit
VCC DC Supply Voltage -0.5 to +70 V
Vin DC Input Voltage -0.5 to +70 V
Vout DC Output Voltage -0.5 to +70
-0.5 to VCC +0.5
V
IIk Input Diode Current -20 mA
IOK Output Diode Current (VOUT VCC ±20 mA
Iout DC Output Current,per Pin ±25 mA
ICC DC Supply Current,VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air,QFN Packages 500 mW
Tstg Storage Temperature -65 to +150

Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. Functional operation should be restricted to the Recommended Operating Conditions.

NLSF3T125 Features

`High Speed: tPD  = 3.8 ns (Typ) at VCC  = 5.0 V
`Low Power Dissipation: ICC  = 4.0 A (Max) at TA = 25
`TTL-Compatible Inputs: VIL  = 0.8 V; VIH = 2.0 V
`Power Down Protection Provided on Inputs
`Balanced Propagation Delays

`Designed for 2.0 V to 5.5 V Operating Range
`Low Noise: VOLP = 0.8 V (Max)
`Pin and Function Compatible with Other Standard Logic Families
`Latchup Performance Exceeds 300 mA

`ESD Performance:Human Body Model; > 2000 V,
                                        Machine Model; > 200 V

`Chip Complexity: 72 FETs or 18 Equivalent Gates

NLSF3T125 Connection Diagram

NLSF3T125  Connection Diagram

NLSF3T125 datasheet

NLSF3T125
PDF/DataSheet Download

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