OCX256

The OCX256 SRAM-based devices are non-blocking 128 X 128 digital crosspoint switches and are available in LVDS (Low Voltage Differential Signaling) and LVPECL (Low Voltage PECL) versions. Both devices are capable of data rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports.The input ports support flow-through mode only. The output ports are individually programmable to operate in either flow-through (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global clock or a next neighbor clock source.

The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a traditional n:1 multiplexer architecture. The OCX256 support various operating modes covering one input to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on all unchanged data paths.

The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch matrix. Readback is supported for device test and verification purposes. The OCX256 also supports the industry standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to download configuration data to the device and readback data. A functional block diagram of the OCX256 is shown in Figure 1.