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P4C1049L

Features: ` High Speed (Equal Access and Cycle Times)- 15/20/25 ns (Commercial)- 20/25/35 ns (Industrial)- 20/25/35/45/55/70 ns (Military)` Low Power` Single 5V±10% Power Supply` Easy Memory Expansion Using CE and OE` Inputs` Common Data I/O` Three-State Outputs` FUNCTIONAL BLOCK DIAGRAM PIN CONFI...

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SeekIC No. : 004439259 Detail

P4C1049L: Features: ` High Speed (Equal Access and Cycle Times)- 15/20/25 ns (Commercial)- 20/25/35 ns (Industrial)- 20/25/35/45/55/70 ns (Military)` Low Power` Single 5V±10% Power Supply` Easy Memory Expansi...

P4C1049L Data Sheet

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Part Number:
P4C1049L
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` High Speed (Equal Access and Cycle Times)
- 15/20/25 ns (Commercial)
- 20/25/35 ns (Industrial)
- 20/25/35/45/55/70 ns (Military)
` Low Power
` Single 5V±10% Power Supply
` Easy Memory Expansion Using CE and OE
` Inputs
` Common Data I/O
` Three-State Outputs
` FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS 1519B
` Fully TTL Compatible Inputs and Outputs
` Advanced CMOS Technology
` Automatic Power Down
` Packages
-36-Pin SOJ (400 mil)
-36-Pin FLATPACK
-36-Pin LCC (452 mil x 920 mil)


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
Vcc Power Supply Pin with
Respect to GND		 0.5 to +7 V
VTERM Terminal Voltage with
Respect to GND
(up to 7.0V)		 0.5 to
VCC +0.5		 V
TA Operating Temperature 55 to +125 °C



Description

The P4C1049 is a 4 Megabit high-speed CMOS static RAM organized as 512Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply.

Access times as fast as 15 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1049 is a member of a family of PACE RAM™ products offering fast access times.

The P4C1049 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A18. Reading is accomplished by device selection (CE) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data of P4C1049 in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW.




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