P89C51RB2HBA General Description
P89C51RB2HBA Maximum Ratings
P89C51RB2HBA Features
• 80C51 Central Processing Unit
• On-chip Flash Program Memory with In-System Programming
(ISP) and In-Application Programming (IAP) capability
• Boot ROM contains low level Flash programming routines for
downloading via the UART
• Can be programmed by the end-user application (IAP)
• 6 clocks per machine cycle operation (standard)
• 12 clocks per machine cycle operation (optional)
• Speed up to 20 MHz with 6 clock cycles per machine cycle
(40 MHz equivalent performance); up to 33 MHz with 12 clocks
per machine cycle
• Fully static operation
• RAM expandable externally to 64 kB
• 4 level priority interrupt
• 8 interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART
Framing error detection
Automatic address recognition
• Power control modes
Clock can be stopped and resumed
Idle mode
Power down mode
• Programmable clock out
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Programmable Counter Array (PCA)
PWM
Capture/compare
P89C51RB2HBA Connection Diagram
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