P89C51RD2BN/01 General Description
P89C51RD2BN/01 Maximum Ratings
P89C51RD2BN/01 Features
• 80C51 Central Processing Unit
• On-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability
• Boot ROM contains low level Flash programming routines for downloading via the UART
• Can be programmed by the end-user application (IAP)
• Parallel programming with 87C51 compatible hardware interface to programmer
• Supports 6-clock/12-clock mode via parallel programmer (default
clock mode after ChipErase is 12-clock)
• 6-clock/12-clock mode Flash bit erasable and programmable via ISP
• 6-clock/12-clock mode programmable "on-the-fly" by SFR bit
• Peripherals (PCA, timers, UART) may use either 6-clock or
12-clock mode while the CPU is in 6-clock mode
• Speed up to 20 MHz with 6-clock cycles per machine cycle(40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle
• Fully static operation
• RAM expandable externally to 64 kbytes
• Four interrupt priority levels
• Seven interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART
Framing error detection
Automatic address recognition
• Power control modes
Clock can be stopped
Idle mode
Power down mode
• Programmable clock-out pin
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Programmable Counter Array (PCA)
PWM
Capture/compare
P89C51RD2BN/01 Connection Diagram
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