PACVGA105

• 7 channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD requirements (8kV contact discharge)
• Very low loading capacitance from ESD protection diodes at less than 5pF typical
• TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines
• Three independent supply pins (VCC, VRGB and VAUX) to facilitate operation with sub-micron Graphics Controller ICs
• High impedance pull-ups (50k nominal to VAUX) for HSYNC and VSYNC inputs
• Pull-up resistors (1.8k nominal to VCC) for DDC_CLK and DDC_DATA lines
• Compact 16-pin QSOP package
• Lead-free version available

The PACVGA105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection of PACVGA105 is implemented with current stering diodes designed to safely handle the high peak surge currents associated with the IEC-1000-4-2  Level-4 ESD Protection Standard (8kV contact discharge). When the channels of PACVGA105 are subjected to an electrostatic discharge, the ESD current pulse is diverted  via the protection diodes into the positive supply rails or ground where they may be safely dissipated.

The upper ESD PACVGA105 diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels of PACVGA105 are connected to the main 5V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance.

Two non-inverting buffers are also included in this IC PACVGA105 for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC. PACVGA105 have a nominal 60 output impedance to match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of PACVGA105 also have high impedance pull-ups (50k nom.) pulling up to the VAUX rail. In addition, the DDC_CLOCK and DDC_DATA channels have 1.8k resistors pulling these inputs up to the main 5V (VCC) rail.