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PCD5002A

Features: ` Wide operating supply voltage range: 1.5 to 6.0 V` EEPROM programming requires only 2.0 V supply` Low operating current: 50 mA typ. (ON), 25 mA typ. (OFF)` Temperature range -25 to +70 °C` CCIR radio paging Code No. 1 (POCSAG) compatible` Supports Advanced Pager Operator's Code Phase...

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PCD5002A: Features: ` Wide operating supply voltage range: 1.5 to 6.0 V` EEPROM programming requires only 2.0 V supply` Low operating current: 50 mA typ. (ON), 25 mA typ. (OFF)` Temperature range -25 to +70 °...

PCD5002A Data Sheet

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Part Number:
PCD5002A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

` Wide operating supply voltage range: 1.5 to 6.0 V
` EEPROM programming requires only 2.0 V supply
` Low operating current: 50 mA typ. (ON), 25 mA typ. (OFF)
` Temperature range -25 to +70 °C
` "CCIR radio paging Code No. 1" (POCSAG) compatible
` Supports Advanced Pager Operator's Code Phase 1 (APOC1) for extended battery economy
` 512, 1200 and 2400 bits/s data rates using 76.8 kHz crystal
` Built-in data filter (16 times oversampling) and bit clock recovery
` Advanced ACCESSâ synchronization algorithm
` 2-bit random and (optional) 4-bit burst error correction
` Up to 6 user addresses Receiver Identity Codes (RICs), each with 4 functions/alert cadences
` Optional automatic call termination when bit error rate is high
` Up to 6 user address frames, independently programmable
` Standard POCSAG sync word, plus up to 4 user programmable sync words
` Continuous data decoding upon reception of user programmable sync word (optional)
` Received data inversion (optional)
` Call alert via beeper, vibrator or LED
` 2-level acoustic alert using single external transistor
` Alert control: automatic (POCSAG type), via cadence register or alert input pin
` Separate power control of receiver and RF oscillator for battery economy
` Dedicated pin for easy control of superheterodyne receiver
` Synthesizer set-up and control interface (3-line serial)
` On-chip EEPROM for storage of user addresses (RICs), pager configuration and synthesizer data
` On-chip SRAM buffer for message data
` Slave I2C-bus interface to microcontroller for transfer of message data, status/control and EEPROM programming (data transfer at up to 100 kbits/s)
` Wake-up interrupt for microcontroller, programmable polarity
` Direct and I2C-bus control of operating status (ON/OFF)
` Battery-low indication (external detector)
` Out-of-range condition indication
` Real-time clock reference output
` On-chip voltage doubler
` Interfaces directly to UAA2080 and UAA2082 paging receivers.


Application

· Advanced display pagers (POCSAG and APOC1)
· Basic alert-only pagers
· Information services
· Personal organizers
· Telepoint
· Telemetry/data transmission.




Pinout

Connection Diagram


Description

The PCD5002A is a very low power pager decoder and controller, capable of handling both standard POCSAG and the advanced APOC1 code. Continuous data decoding upon reception of a dedicated sync word is available for news pager applications.

Data rates supported are 512, 1200 and 2400 bits/s using a single 76.8 kHz crystal. On-chip EEPROM PCD5002A is programmable using a minimum supply voltage of 2.0 V, allowing 'over-the-air' programming. I2C-bus compatible.




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