PCF8562

Features:

•Single-chip LCD controller/driver
•Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing
•Selectable display bias configuration: static, 1/2 and 1/3
•Internal LCD bias generation with voltage-follower buffers
•32 segment drives: up to sixteen 8-segment numeric characters; up to eight 15-segment alphanumeric characters; or any graphics of up to 128 elements
•32 × 4-bit RAM for display data storage
•Auto-incremental display data loading across device subaddress boundaries
•Display memory bank switching in static and duplex drive modes
•Versatile blinking modes
•Independent supplies possible for LCD and logic voltages
•Wide power supply range: from 1.8 to 5.5 V
•Wide logic LCD supply range: from 2.5 V for low-threshold LCDs and up to 6.5 V for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs
•Low power consumption
•400 kHz I2C-bus interface
•TTL/CMOS compatible
•Compatible with 4, 8 or 16-bit microprocessors or microcontrollers
•No external components
•Compatible with chip-on-glass technology
•Manufactured in silicon gate CMOS process.


Pinout




Specifications

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
VDD	supply voltage	-0.5	+6.5	V
VLCD	LCD supply voltage	VSS - 0.5	+7.5	V
Vi1	input voltage T1, T3, SA0 and OSC	VSS - 0.5	VDD + 0.5	V
Vi2	input voltage SDA and SCL	VSS - 0.5	+6.5	V
Vo	output voltage T2 and SDA	VSS - 0.5	VDD + 0.5	V
Vo	output voltage R1 to R40 and C1 to C101	VLCD - 0.5	VDD + 0.5	V
II	DC input current	-10	+10	mA
IO	DC output current	-10	+10	mA
IDD	VDD current	-50	+50	mA
ISS	VSS current	-50	+50	mA
ILCD	VLCD current	-50	+50	mA
Ptot	total power dissipation	-	400	mW
PO	power dissipation per output	-	100	mW
Tstg	storage temperature	-65	+150

Description

The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. PCF8562 generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes).