Purchase PEB20320, In-stock PEB20320 From SeekIC.
Package Cooled:QFP160
- Table of contents:
PEB20320
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DataSheet
General Description
PEB20320 Maximum Ratings
| Parameter |
Symbol |
Limit Values |
Unit | ||
|
min. |
max. | ||||
| Ambient temperature under bias: PEB PEF |
TA TA |
0 40 |
70 85 |
°C | |
| Storage temperature |
Tstg |
65 |
125 |
°C | |
| Voltage at any pin with respect to ground |
VS |
0.4 |
VDD + 0.4 |
V | |
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
PEB20320 Features
• Serial Interface
Up to 32 independent communication channels.
Serial multiplexed (full duplex) input/output for 2048-, 4096-, 1544- or 1536-Kbit/s PCM highways.
• Dynamic Programmable Channel Allocation
Compatible with T1/DS1 24-channel and CEPT 32-channel PCM byte format.
Concatenation of any, not necessarily consecutive, time slots to superchannels independently for receive and transmit direction.
Support of H0, H11, H12 ISDN-channels.
Subchanneling on each time slot possible.
• Bit Processor Functions (adjustable for each channel)
HDLC Protocol
Automatic flag detection and transmission
Shared opening and closing flag
Detection of interframe-time-fill change, generation of interframe-time-fill '1's or flags
Zero bit insertion
Flag stuffing and flag adjustment for rate adaption
CRC generation and checking (16 or 32 bits)
Transparent CRC option per channel and/or per message
Error detection (abort, long frame, CRC error, 2 categories of short frames, non-octet frame content)
Special short frame mode to allow reception of 'frames' with a least on byte length
ABORT/IDLE generation
V.110/X.30 Protocol
Automatic synchronization in receive direction, automatic generation of the synchronization pattern in transmit direction
E / S / X bits freely programmable in transmit direction, van be changed during transmission; changes monitored and reported in receive direction
Generation/detection of loss of synchronism
Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s
Transparent Mode A
Slot synchronous transparent transmission/reception without frame structure
Bit-overwrite with fill/mask bits
Flag generation, flag stuffing, flag extraction, flag generation in the abort case with programmable flag
Transparent Mode B
Transparent transmission/reception in frames delimited by 00H flags
Shared opening and closing flag
Flag stuffing, flag detection, flag generation in the abort case
Error detection (non octet frame content, short frame, long frame)
Transparent Mode R
Transparent transmission/reception with GSM 08.60 frame structure
Automatic 0000H flag generation/detection
Support of 40, 391/2, 401/2 octet frames
Error detection (non octet frame content, short frame, long frame)
Protocol Independent
Channel inversion (data, flags, IDLE code)
Format conventions as in CCITT Q.921 § 2.8
Data over- and underflow detected
• Processor Interface
ON-CHIP 64-channel DMA controller with buffer chaining capability.
Compatible with Motorola 68020 processor family and Intel 32-bit processor (80386).
32 bit data bus and 32 bit address bus (4 Gbyte RAM addressable, Motorola and Intel non-parity) or 28 bit address bus (256 Mbyte RAM addressable, Intel parity)
Intel parity mode with data byte parity (4 parity bits)
Parity check for read accesses
Parity generation for write accesses
Interrupt-circular buffer with variable size
Maskable interrupts for each channel
µP interface buffer of depth 16 long words for adaptive bus occupation
• General
Connection of up to four MUNICH32 supporting a
128-channel basic access D-channel controller.
ON-CHIP receive and transmit data buffer; the buffer size is 256 bytes each.
HDLC protocol or transparent mode, support of ECMA 102, CCITT I4.63 RA2,
V.110, X.30, DMI mode 0, 1, 2 (bit rate adaption), GSM 08.60 TRAU frames.
LOOP mode, complete loop as well as single channel loop
JTAG boundary scan test
Advanced low-power CMOS technology
TTL-compatible inputs/outputs
160 pin P-MQFP package
Up to 32 independent communication channels.
Serial multiplexed (full duplex) input/output for 2048-, 4096-, 1544- or 1536-Kbit/s PCM highways.
• Dynamic Programmable Channel Allocation
Compatible with T1/DS1 24-channel and CEPT 32-channel PCM byte format.
Concatenation of any, not necessarily consecutive, time slots to superchannels independently for receive and transmit direction.
Support of H0, H11, H12 ISDN-channels.
Subchanneling on each time slot possible.
• Bit Processor Functions (adjustable for each channel)
HDLC Protocol
Automatic flag detection and transmission
Shared opening and closing flag
Detection of interframe-time-fill change, generation of interframe-time-fill '1's or flags
Zero bit insertion
Flag stuffing and flag adjustment for rate adaption
CRC generation and checking (16 or 32 bits)
Transparent CRC option per channel and/or per message
Error detection (abort, long frame, CRC error, 2 categories of short frames, non-octet frame content)
Special short frame mode to allow reception of 'frames' with a least on byte length
ABORT/IDLE generation
V.110/X.30 Protocol
Automatic synchronization in receive direction, automatic generation of the synchronization pattern in transmit direction
E / S / X bits freely programmable in transmit direction, van be changed during transmission; changes monitored and reported in receive direction
Generation/detection of loss of synchronism
Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s
Transparent Mode A
Slot synchronous transparent transmission/reception without frame structure
Bit-overwrite with fill/mask bits
Flag generation, flag stuffing, flag extraction, flag generation in the abort case with programmable flag
Transparent Mode B
Transparent transmission/reception in frames delimited by 00H flags
Shared opening and closing flag
Flag stuffing, flag detection, flag generation in the abort case
Error detection (non octet frame content, short frame, long frame)
Transparent Mode R
Transparent transmission/reception with GSM 08.60 frame structure
Automatic 0000H flag generation/detection
Support of 40, 391/2, 401/2 octet frames
Error detection (non octet frame content, short frame, long frame)
Protocol Independent
Channel inversion (data, flags, IDLE code)
Format conventions as in CCITT Q.921 § 2.8
Data over- and underflow detected
• Processor Interface
ON-CHIP 64-channel DMA controller with buffer chaining capability.
Compatible with Motorola 68020 processor family and Intel 32-bit processor (80386).
32 bit data bus and 32 bit address bus (4 Gbyte RAM addressable, Motorola and Intel non-parity) or 28 bit address bus (256 Mbyte RAM addressable, Intel parity)
Intel parity mode with data byte parity (4 parity bits)
Parity check for read accesses
Parity generation for write accesses
Interrupt-circular buffer with variable size
Maskable interrupts for each channel
µP interface buffer of depth 16 long words for adaptive bus occupation
• General
Connection of up to four MUNICH32 supporting a
128-channel basic access D-channel controller.
ON-CHIP receive and transmit data buffer; the buffer size is 256 bytes each.
HDLC protocol or transparent mode, support of ECMA 102, CCITT I4.63 RA2,
V.110, X.30, DMI mode 0, 1, 2 (bit rate adaption), GSM 08.60 TRAU frames.
LOOP mode, complete loop as well as single channel loop
JTAG boundary scan test
Advanced low-power CMOS technology
TTL-compatible inputs/outputs
160 pin P-MQFP package
PEB20320 Connection Diagram
PEB20320
PDF/DataSheet Download
- Datasheet: PEB20320
- File Size: 2312434 KB
- Manufacturer: INFINEON [Infineon Technologies AG]
- Click here to Download
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