Position: Home  > All Categories> Integrated Circuits (ICs) > PEB20571

PEB20571

Features: DELIC-LC is optimized for line card applications:• One IOM-2000 interface supporting three VIPs i.e. up to 24 ISDN channels• Two IOM-2 (GCI) ports (configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers• Four PCM ports with up to 4 x 2.048...

product image

PEB20571 Picture
See larger image
SeekIC No. : 004457985 Detail

PEB20571: Features: DELIC-LC is optimized for line card applications:• One IOM-2000 interface supporting three VIPs i.e. up to 24 ISDN channels• Two IOM-2 (GCI) ports (configurable as PCM ports) s...

PEB20571 Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
PEB20571
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2025/12/28

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

DELIC-LC is optimized for line card applications:
• One IOM-2000 interface supporting three VIPs i.e. up to 24 ISDN channels
• Two IOM-2 (GCI) ports (configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers
• Four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s
• Switching matrix 256 x 256 TS (8-bit switching)
• 24 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
• Serial communication controller: high-speed signaling channel for 2.048 Mbit/s
• General purpose I/O ports
• Standard multiplexed and de-multiplexed µP interface: Infineon, Intel, Motorola
• Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source
• JTAG compliant test interface
• single 3.3 V power supply, 5 V tolerant inputs
1.2 DELIC-PB Key Features
Compared to the DELIC-LC, having a fixed functionality, the DELIC-PB provides a high degree of flexibility (in terms of selected number of ports or channels). Additionally it features computing power for typical DSP-oriented PBX tasks like conferencing, DTMF etc. A Microsoft Windows based configuration tool, the Configurator, enables to generate an application specific functionality. Its features are mainly determined by the firmware of the integrated telecom DSP. List of maximum available features:
• One IOM-2000 interface supporting up to three VIPs i.e. up to 24 ISDN channels
• Support of DASL mode
• Up to two IOM-2 (GCI) ports (also configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers
• Up to four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s
• Switching matrix 256 x 256 TS (switching of 4-/8- bit time slots)
• Up to 32 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
• Up to 4 serial communication controllers: one of them with up to 8.192 Mbit/s data rate
• General purpose I/O ports
• DECT synchronization support
• Standard multiplexed and de-multiplexed µP interface: Infineon, Intel, Motorola
• Dedicated DMA support mailbox for 2 DMA-channels
• Integrated DSP core OAK+ (60 MIPS for layer 1 control, signalling and DSPalgorithms)
• 4 kWord on-chip program memory
• 2 kWord on-chip data memory
• 2 kWord ROM
• DSP work load measurement for run-time statistics, DSP alive indication
• On chip debugging unit
• Serial DSP program debugging interface connected via JTAG port
• A-/µ-law conversion unit
• Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source
• JTAG compliant test interface
• single 3.3 V power supply, 5 V compatible inputs
Note: As each feature consumes system resources (DSP-MIPS, memory, port pins), the
maximum available number of supported interfaces or HDLC channels is limited
by the totally available resources. A System Configurator tool (see DELIC
Software User's Manual) helps to determine a valid configuration.


Pinout

Connection Diagram


Specifications

Parameter

Symbol

Limit Values

Unit

Storage temperature
Tstg
65 to 150
°C
IC supply voltage
VDD
0.3 to 4.6
V
DC input voltage (except I/O)
VI
0.3 to 6.0
V
DC output voltage (including I/O);
output in high or low state
VO
0.3 to VDD + 0.3
V
DC output voltage (including I/O);
output in tri-state
VI, VO
0.3 to 6.0
V
ESD robustness1)
HBM: 1.5 kΩ, 100 pF
V ESD,HBM
2000
V
1) According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
The Pins (TBD) are not protected against voltage stress > (TDB) V (versus VS or GND). The (TBD)
performance prohibits the use of adequate protective structures.
Note: Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values
may cause irreversible damage to the integrated circuit.


Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Cables, Wires - Management
NM-SF50+
CCK26.5-MM-190-30
Tapes, Adhesives
803
AC452-2
Fans, Thermal Management
3610ML-05W-B49
1608KL-05W-B39
Power Supplies - Board Mount
HC-06
PM150RSA060-S81AH0G
Integrated Circuits (ICs)
TA8435H
1MB12-140
Resistors
A101G
3006P-1-205LF
View more