Purchase PEB20571, In-stock PEB20571 From SeekIC.
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PEB20571
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DataSheet
General Description
PEB20571 Maximum Ratings
|
Parameter |
Symbol |
Limit Values |
Unit |
| Storage temperature |
Tstg |
65 to 150 |
°C |
| IC supply voltage |
VDD |
0.3 to 4.6 |
V |
| DC input voltage (except I/O) |
VI |
0.3 to 6.0 |
V |
| DC output voltage (including I/O); output in high or low state |
VO |
0.3 to VDD + 0.3 |
V |
| DC output voltage (including I/O); output in tri-state |
VI, VO |
0.3 to 6.0 |
V |
| ESD robustness1) HBM: 1.5 kΩ, 100 pF |
V ESD,HBM |
2000 |
V |
The Pins (TBD) are not protected against voltage stress > (TDB) V (versus VS or GND). The (TBD)
performance prohibits the use of adequate protective structures.
Note: Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values
may cause irreversible damage to the integrated circuit.
PEB20571 Features
DELIC-LC is optimized for line card applications:
• One IOM-2000 interface supporting three VIPs i.e. up to 24 ISDN channels
• Two IOM-2 (GCI) ports (configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers
• Four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s
• Switching matrix 256 x 256 TS (8-bit switching)
• 24 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
• Serial communication controller: high-speed signaling channel for 2.048 Mbit/s
• General purpose I/O ports
• Standard multiplexed and de-multiplexed µP interface: Infineon, Intel, Motorola
• Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source
• JTAG compliant test interface
• single 3.3 V power supply, 5 V tolerant inputs
1.2 DELIC-PB Key Features
Compared to the DELIC-LC, having a fixed functionality, the DELIC-PB provides a high degree of flexibility (in terms of selected number of ports or channels). Additionally it features computing power for typical DSP-oriented PBX tasks like conferencing, DTMF etc. A Microsoft Windows based configuration tool, the Configurator, enables to generate an application specific functionality. Its features are mainly determined by the firmware of the integrated telecom DSP. List of maximum available features:
• One IOM-2000 interface supporting up to three VIPs i.e. up to 24 ISDN channels
• Support of DASL mode
• Up to two IOM-2 (GCI) ports (also configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers
• Up to four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s
• Switching matrix 256 x 256 TS (switching of 4-/8- bit time slots)
• Up to 32 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
• Up to 4 serial communication controllers: one of them with up to 8.192 Mbit/s data rate
• General purpose I/O ports
• DECT synchronization support
• Standard multiplexed and de-multiplexed µP interface: Infineon, Intel, Motorola
• Dedicated DMA support mailbox for 2 DMA-channels
• Integrated DSP core OAK+ (60 MIPS for layer 1 control, signalling and DSPalgorithms)
• 4 kWord on-chip program memory
• 2 kWord on-chip data memory
• 2 kWord ROM
• DSP work load measurement for run-time statistics, DSP alive indication
• On chip debugging unit
• Serial DSP program debugging interface connected via JTAG port
• A-/µ-law conversion unit
• Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source
• JTAG compliant test interface
• single 3.3 V power supply, 5 V compatible inputs
Note: As each feature consumes system resources (DSP-MIPS, memory, port pins), the
maximum available number of supported interfaces or HDLC channels is limited
by the totally available resources. A System Configurator tool (see DELIC
Software User's Manual) helps to determine a valid configuration.
• One IOM-2000 interface supporting three VIPs i.e. up to 24 ISDN channels
• Two IOM-2 (GCI) ports (configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers
• Four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s
• Switching matrix 256 x 256 TS (8-bit switching)
• 24 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
• Serial communication controller: high-speed signaling channel for 2.048 Mbit/s
• General purpose I/O ports
• Standard multiplexed and de-multiplexed µP interface: Infineon, Intel, Motorola
• Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source
• JTAG compliant test interface
• single 3.3 V power supply, 5 V tolerant inputs
1.2 DELIC-PB Key Features
Compared to the DELIC-LC, having a fixed functionality, the DELIC-PB provides a high degree of flexibility (in terms of selected number of ports or channels). Additionally it features computing power for typical DSP-oriented PBX tasks like conferencing, DTMF etc. A Microsoft Windows based configuration tool, the Configurator, enables to generate an application specific functionality. Its features are mainly determined by the firmware of the integrated telecom DSP. List of maximum available features:
• One IOM-2000 interface supporting up to three VIPs i.e. up to 24 ISDN channels
• Support of DASL mode
• Up to two IOM-2 (GCI) ports (also configurable as PCM ports) supporting up to 16 ISDN channels or 32 analog subscribers
• Up to four PCM ports with up to 4 x 2.048 Mbit/s (4 x 32 TS) or 2 x 4.096 Mbit/s or 1 x 8.192 Mbit/s
• Switching matrix 256 x 256 TS (switching of 4-/8- bit time slots)
• Up to 32 HDLC controllers assignable to any D- or B-channel (at 16 kbit/s or 64 kbit/s)
• Up to 4 serial communication controllers: one of them with up to 8.192 Mbit/s data rate
• General purpose I/O ports
• DECT synchronization support
• Standard multiplexed and de-multiplexed µP interface: Infineon, Intel, Motorola
• Dedicated DMA support mailbox for 2 DMA-channels
• Integrated DSP core OAK+ (60 MIPS for layer 1 control, signalling and DSPalgorithms)
• 4 kWord on-chip program memory
• 2 kWord on-chip data memory
• 2 kWord ROM
• DSP work load measurement for run-time statistics, DSP alive indication
• On chip debugging unit
• Serial DSP program debugging interface connected via JTAG port
• A-/µ-law conversion unit
• Programmable PLL based Master/Slave clock generator, providing all system clocks from a single 16.384 MHz crystal source
• JTAG compliant test interface
• single 3.3 V power supply, 5 V compatible inputs
Note: As each feature consumes system resources (DSP-MIPS, memory, port pins), the
maximum available number of supported interfaces or HDLC channels is limited
by the totally available resources. A System Configurator tool (see DELIC
Software User's Manual) helps to determine a valid configuration.
PEB20571 Connection Diagram
PEB20571
PDF/DataSheet Download
- Datasheet: PEB20571
- File Size: 174871 KB
- Manufacturer: INFINEON [Infineon Technologies AG]
- Click here to Download
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