PEB2086

·Full duplex 2B + D S/T interface transceiver according to CCITT I.430
·Conversion of the frame structure between the S/T interface and IOM
·Receive timing recovery according to selected operating mode
·D-channe·access control
·Activation and deactivation procedures, with automatic wake-up from power-down state
·Access to S and Q bits of S/T interface
·Adaptively switched receive thresholds
·Frame alignment with absorption of phase wander in NT2 network side applications
·Support of LAPD protocol
·FIFO buffer (2 ´ 64 bytes) for efficient transfer of D-channel packets
·8-bit microprocessor interface, multiplexed or non-multiplexed
·Serial interfaces: IOM-1, SLD, SSI IOM-2
·Implementation of IOM-1/IOM-2 MONITOR and C/I channel protocol to control peripheral devices
·mP access to B-channels and intercommunication channels
·B-channel switching
·Watchdog timer
·Test loops
·Advanced CMOS technology
·Low power consumption: standby 8 mW active 80 mW