PEB3456

• Protocol processing on a channelized or unchannelized DS3 link for frame relay or router applications
• Direct connection to DS3 line interface unit or DS3 to STS-1 mapper
• Support of 256 bidirectional channels, which can be assigned arbitrarily to a maximum of 28 links, for HDLC, PPP or transparent mode (TMA) processing
• Concatenation of any, not necessarily consecutive, time slots to logical channels on each physical link. Supports DS0, fractional T1/E1 or T1/E1 channels
• Provides 32kB data buffer in transmit direction and 12kB data buffer in receive direction
• Integrates 28T1/21E1 framers (frame alignment function) and 28T1/21E1 signalling controllers
• Integrates a DS2/DS3 multiplexer and framer
• Remote loopbacks selectable for either DS3 signal, DS2 signal or T1/E1 signal/ payload
• System interface is a PCI 32 bit, 66 MHz Rev. 2.1 compliant bus interface, which supports configuration of subsystem ID / subsystem vendor ID via a serial EEPROM interface. PCI bus interface can be operated in the range of 33 MHz to 66 MHz
• Integrates a local microprocessor master and slave interface (demultiplexed 16 bit address and data bus in Intel mode or Motorola mode) which allows access to the local bus via the PCI bus or which can communicate with a PCI host processor through an on-chip mailbox
• For debugging purposes optional access to the framer and signalling controller functions via the PCI interface
• JTAG boundary scan according to IEEE1149.1 (5 pins).
• 0.25 µm, 2.5V core technology
• I/Os are 3.3V tolerant and have 3.3V driving capability
• Package P-BGA 388 (35mm x 35mm; pitch 1.27mm)
• Full scan path and BIST of on-chip RAMs for production test
• Performance: 45Mbit/s (DS3) throughput per direction
• Estimated power consumption: 2W
• Also available as device with extended temperature range -40..+85°C