PI90SD1636A

The PI90SD1636A is a single chip, Gigabit Ethernet transceiver. It performs all the functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specified by the IEEE 802.3z Gigabit Ethernet standard. These functions of PI90SD1636A include parallel-to-serial and serial-to-parallel conversion, clock generation, clock data recovery, and word synchronization. In addition, an internal loopback function is provided for system debugging.

The PI90SD1636A is ideal for Gigabit Ethernet, serial backplane and proprietary point-to-point applications. The device supports 1000BASE-LX and 1000BASE-SX fiber-optic media, and 1000BASE-CX copper media.

The transmitter section of the PI90SD1636A accepts 10-bit wide parallel TTL data and converts it to a high speed serial data stream. The parallel data is encoded in 8b/10b format. This incoming parallel data is latched into an input register, and synchronized on the rising edge of the 125 MHz reference clock supplied by the user. A phase locked loop (PLL) locks to the 125 MHz clock. The clock is then multiplied by 10 to produce a 1.25 GHz serial clock that is used to provide the high speed serial data output. The output is sent through a Pseudo Emitter Coupled Logic (PECL) driver. This output connects directly to a copper cable in the case of 1000BASE-CX medium, or to a fiber optic module in the case of 1000BASE-LX or 1000BASE SX fiber optic medium.

The receiver section of the PI90SD1636A accepts a serial PECL-compatible data stream at a 1.25 Gbps rate, recovers the original 10-bit wide parallel data format, and retimes the data. A PLL locks onto the incoming serial data stream, and recovers the 1.25 GHz high speed serial clock and data. This is accomplished by continually frequency locking onto the 125 MHz reference clock, and by phase locking onto the incoming data stream. The serial data is converted back to parallel data format. The 'comma' character is used to establish byte alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are alternately used to clock out the parallel data on the rising edge. This parallel data is sent to the user in TTL-compatible form.