PLS167-33

The PLS167-33 is one member of the PLS167 series.The PLS167 is field-programmable replacements for sequential logic. The devices function as Mealy state machines with a registered output. The PLS utilizes the familiar AND/OR PLA logic structure to implement  sum-of-product equations. Both arrays are user-programmable to implementtransition terms causing changes in the infernal state registeror output register.The PLS167-33 devices are fabricated in Advanced Micro Devices' advanced oxide-isolated bipolar process.

Features of the PLS167-33 are:(1)field-programmable replacement for sequential control logic; (2)advanced mealy state machine/sequencer architecture; (3)programmable ANDlprogrammable OR array for flexibility; (4)full drive: 24 mA lol, three-state outputs; (5)user-programmable pin for asynchronous flip-flop preset/output enable; (6)automatic "Hold" state via S-R flip-flops; (7)security bit hides proprietary designs from competitors; (8)supported by PALASM software and standard PLD programmers; (9)available in 24-pin plastic SKINNYDIP and 28-pin PLCC packages; (10)fabricated with high-performance bipolar and electrically erasable CMOS technology.The PLS devices are fully supported by industry-standard CAD tools, including the PALASM design software package. Device programming is accomplished by using standard PLD programmers.

The absolute maximum ratings of the PLS167-33 can be summarized as:(1)supply voltage with respect to ground:-0.5 to 7.0 V;(2)DC input voltage:-0.5 to 5.5V;(3)DC output or I/O pin voltage:-0.5 to 5.5V;(4)storage temperature:-65 to 150;(5)ambient temperature operating in free air:0 to 75;(6)DC output current:16 mA.The Preset input can be converted to a three-state Output Enable function by an architecture bit. Expansion to larger control functions can be accommodated by connetting several PLS devices to a control bus and selectively enabling them to each handle a segment of the control algorithm. This user-programmable option is specified as an auxiliary equation in the design file or optionally by use of a keyword.All transition terms can include True, False, or Don't Care states of the controlling variables. The OR array merges one or more product terms to generate the desired user logic functions for the output and next-state registers. This sharing of OR-terms minimizes the over-all logic required to implement complicated control functions.