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Part Number: PSB7280
Description: The PSB 7280 Joint Audio Decoder Encoder is a device which implements voice compression algorithms usi...
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PSB7280
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General Description
PSB7280 General Description
The PSB 7280 Joint Audio Decoder Encoder is a device which implements voice compression algorithms using the Low-Delay Code Excited Linear Prediction (LD-CELP) standard as defined in the ITU-T G.728 Recommendation, and for 7-kHz voice using the Sub-Band Coded Adaptive Differential PCM (SBC-ADPCM) coding according to the G.722 Recommendation. In addition G.711 PCM audio coding is also supported.
Thus in the G.728 mode it compresses a digitized PCM (64 kbit/s) or linear (128 kbit/s) voice signal into a 16 kbit/s bit stream, and vice versa. The algorithm is implemented in 16-bit fixed point arithmetic and complies with the newest fixed point specification set forth by the ITU.
In the G.722 mode it compresses the PCM compressed (128 kbit/s) or the linear uncompressed (256 kbit/s) 7 kHz audio samples into a rate of 48/56/64 kbit/s, and vice versa.
The JADE finds applications in
ISDN Videophones (H.320)
Video Conference Systems
Corporate Network voice concentrators, multiplexers and gateways
Data-over-voice and Voice-over-data terminals.
Other potential application areas are:
Networks (e.g. LANs) for packetized voice
Digital Added Main-Line (DAML) & Digital Circuit Multiplication Equipment (DCME)
Voice storage e.g. in PC based applications
Message recording and distribution.
The interfaces of the JADE allow a seamless integration into IOM-2 based systems.
After the circuit is set up in the proper mode of operation and parameter settings are programmed by a controlling software, the circuit runs independently of the rest of the system. Status and control information to/from the JADE can be transferred either inband the compressed audio data via the corresponding selected interface or outband using an 8-bit parallel host interface.
In a Videophone system using the 8 ´ 8 (formerly IIT) VCP (Video Codec and Multimedia Communications Processor) the Siemens PSB 7280 can work standalone without the need of external initialization. The default configuration of the JADE is such, that no host is needed in this case and the full communication is done between the VCP and the
Siemens PSB 7280.
The voice compression algorithms are implemented by an embedded 16-bit fixed point Digital Signal Processor with all memories internal and no external memory needed.
PSB7280 Maximum Ratings
|
Parameter |
Symbol |
Limit Values |
Units |
| Ambient temperature under bias |
TA |
0 to 70 |
|
| Storage temperature |
Tstg |
65 to 125 |
|
| Supply Voltage |
VDD |
0.5 to 4.2 |
V |
| Supply Voltage |
VDDA |
0.5to 4.2 |
V |
| Supply Voltage |
VDDP |
0.5to 6.0 |
V |
| Voltage of pin with respect to ground: XTAL1, XTAL2, |
VS |
0.4 to VDDA + 0.5 |
V |
| Voltage on any pin with respect to ground |
VS |
If VDDP < 3 V: 0.4 to VDD + 0.5 If VDDP > 3 V: 0.4 to VDDP + 0.5 |
V V |
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
PSB7280 Features
Functions
`G.728 compression/decompression (16 kbit/s)
`G.722 compression/decompression for 7-kHz audio (64, 56, 48 kbit/s)
`G.711 compression/decompression (64 kbit/s)
`Digital sampling rate conversion (16 kHz - 8 kHz) for G.722 audio with 8-kHz Codec (bandwidth reduced to 3.4 kHz)
` Accepts/outputs uncompressed audio in 8-bit PCM A/m law or 16-bit linear format
`Uncompressed/compressed audio switchable between different interface combinations (IOM/Serial Audio
Interface, IOM/Host, Host/Host)
` Inband controlled H.221/H.223 oriented audio protocol, e.g. for direct serial connection to videocodec (VCP
of 8 ´ 8 Inc., formerly IIT Inc.) as well as host based solutions
`Outband controlled audio protocol with optimized data rate
` Stable reaction on interrupt handshake timing violations of e.g. a slow host (Windows® PC)
System On-chip Functions
` Two universal serial HDLC/transparent data controllers
` IOM-2 monitor and C/I channels
` Generation of programmable system clock output
` Three programmable timers
` Programmable on-chip PLL for internal clock generation from ISDN low frequency (7.68 MHz) clock
Interfaces
` 4-line IOM-2/PCM interface
` 5-line serial audio interface, e.g. for connection to videocodec/H.221/223 processor
` Parallel 8-bit Host interface
` 4-line general purpose interface
` External memory interface to external SRAM with programmable waitstates (0 to 15), for development
purposes only.
Control
` Programmable via parallel host interface
` Operating parameters and mode settings via a register bank
` Access to audio channels and HDLC/serial transparent data controllers from DSP or an external host
` Interface to external software via a full-duplex 256-byte on-chip mailbox
`H.221/H.223 oriented inband configuration/mode switching
General
`Supply voltage: 3.0 - 3.6 V
`Additional 4.5 to 5.5 V supply for connection to 5-V systems without external
components
` Ambient temperature range 0 to + 70
` P-TQFP-100 package
`G.728 compression/decompression (16 kbit/s)
`G.722 compression/decompression for 7-kHz audio (64, 56, 48 kbit/s)
`G.711 compression/decompression (64 kbit/s)
`Digital sampling rate conversion (16 kHz - 8 kHz) for G.722 audio with 8-kHz Codec (bandwidth reduced to 3.4 kHz)
` Accepts/outputs uncompressed audio in 8-bit PCM A/m law or 16-bit linear format
`Uncompressed/compressed audio switchable between different interface combinations (IOM/Serial Audio
Interface, IOM/Host, Host/Host)
` Inband controlled H.221/H.223 oriented audio protocol, e.g. for direct serial connection to videocodec (VCP
of 8 ´ 8 Inc., formerly IIT Inc.) as well as host based solutions
`Outband controlled audio protocol with optimized data rate
` Stable reaction on interrupt handshake timing violations of e.g. a slow host (Windows® PC)
System On-chip Functions
` Two universal serial HDLC/transparent data controllers
` IOM-2 monitor and C/I channels
` Generation of programmable system clock output
` Three programmable timers
` Programmable on-chip PLL for internal clock generation from ISDN low frequency (7.68 MHz) clock
Interfaces
` 4-line IOM-2/PCM interface
` 5-line serial audio interface, e.g. for connection to videocodec/H.221/223 processor
` Parallel 8-bit Host interface
` 4-line general purpose interface
` External memory interface to external SRAM with programmable waitstates (0 to 15), for development
purposes only.
Control
` Programmable via parallel host interface
` Operating parameters and mode settings via a register bank
` Access to audio channels and HDLC/serial transparent data controllers from DSP or an external host
` Interface to external software via a full-duplex 256-byte on-chip mailbox
`H.221/H.223 oriented inband configuration/mode switching
General
`Supply voltage: 3.0 - 3.6 V
`Additional 4.5 to 5.5 V supply for connection to 5-V systems without external
components
` Ambient temperature range 0 to + 70
` P-TQFP-100 package
PSB7280 Connection Diagram
PSB7280
PDF/DataSheet Download
- Datasheet: PSB7280
- File Size: 2230063 KB
- Manufacturer: SIEMENS [Siemens Semiconductor Group]
- Click here to Download
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