PSB 2115

The ISDN PC Adapter Circuit IPAC integrates all necessary functions for a host based ISDN access solution on a single chip.

It includes the S-transceiver (Layer 1), an HDLC controller for the D-channel and two protocol controllers for each B-channel. They can be used for HDLC protocol or transparent access. The system integration is simplified by several host interface configurations selected via pin strapping. They include multiplexed and demultiplexed interface options as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations.

The IPAC combines the functions of the ISDN Subscriber Access Controller (ISAC-S PEB 2086) and the High-Level Serial Communications Controller Extended for Terminals (HSCX-TE PSB 21525) providing additional features and enhanced functionality.

The FIFO size of the B-channel buffers is 2x64 bytes per channel and per direction. The S-transceiver supports other terminal relevant operation modes like line termination subscriber side (LT-S) and line termination trunk side (LT-T). A multi-line ISDN solution to support both S and U (2B1Q) line coding is simplified as well as multi-line solution with up to 3 S-interfaces.

An auxiliary I/O port has been added with interrupt capabilities on two input lines. These programmable I/O lines may be used to connect a DTMF receiver or other peripheral components to the IPAC which need software control or have to forward statusinformation to the host. Peripheral data controllers can transfer data on a PCM interface  which is mapped into the B-channels on the IOM-2 interface.

Three programmable LED outputs can be used to indicate certain status information, one of them is capable to indicate the activation status of the S-interface automatically.

The IPAC is produced in advanced CMOS technology.