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Part Number: PSD4235G2
Description: The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and...
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PSD4235G2
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General Description
PSD4235G2 General Description
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.
PSD4235G2 Maximum Ratings
| Symbol | Parameter | Min. | Max. | Unit |
| TSTG | Storage Temperature | 65 | 125 | °C |
| TLEAD | Lead Temperature during Soldering (20 seconds max.)1 | 235 | °C | |
| VIO | Input and Output Voltage (Q = VOH or Hi-Z) | 0.6 | 7.0 | V |
| VCC | Supply Voltage | 0.6 | 7.0 | V |
| VPP | Device Programmer Supply Voltage | 0.6 | 14.0 | V |
| VESD | Electrostatic Discharge Voltage (Human Body model) 2 | 2000 | 2000 | V |
PSD4235G2 Features
`Dual Bank Flash Memories
4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
256 Kbit Secondary Flash Memory with 4 sectors
Concurrent operation: read from one memory while erasing and writing the other
`64 Kbit SRAM (Battery Backed)
`PLD with macrocells
Over 3000 Gates of PLD: CPLD and DPLD
CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
DPLD user defined internal chip select decoding
`Seven l/O Ports with 52 I/O pins
52 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function l/Os
l/O ports may be configured as open-drain outputs
`In-System Programming (ISP) with JTAG
Built-in JTAG compliant serial port allows fullchip In-System Programmability
Efficient manufacturing allow easy product testing and programming
Use low cost FlashLINK cable with PC
`Page Register
Internal page register that can be used to expand the microcontroller address space by a factor of 256
`Programmable power management
`High Endurance:
100,000 Erase/Write Cycles of Flash Memory
1,000 EraseWrite Cycles of PLD
15 Year Data Retention
`Single Supply Voltage
5V ±10%
`Memory Speed
70ns Flash memory and SRAM access time
4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16)
256 Kbit Secondary Flash Memory with 4 sectors
Concurrent operation: read from one memory while erasing and writing the other
`64 Kbit SRAM (Battery Backed)
`PLD with macrocells
Over 3000 Gates of PLD: CPLD and DPLD
CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
DPLD user defined internal chip select decoding
`Seven l/O Ports with 52 I/O pins
52 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function l/Os
l/O ports may be configured as open-drain outputs
`In-System Programming (ISP) with JTAG
Built-in JTAG compliant serial port allows fullchip In-System Programmability
Efficient manufacturing allow easy product testing and programming
Use low cost FlashLINK cable with PC
`Page Register
Internal page register that can be used to expand the microcontroller address space by a factor of 256
`Programmable power management
`High Endurance:
100,000 Erase/Write Cycles of Flash Memory
1,000 EraseWrite Cycles of PLD
15 Year Data Retention
`Single Supply Voltage
5V ±10%
`Memory Speed
70ns Flash memory and SRAM access time
PSD4235G2 Connection Diagram
PSD4235G2
PDF/DataSheet Download
- Datasheet: PSD4235G2
- File Size: 581411 KB
- Manufacturer: WSI
- Click here to Download
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