PSD4256G6V

  Dual bank Flash memories 8Mbits of Primary Flash Memory (16 uniformsectors, 64Kbyte) 512Kbits of Secondary Flash Memory with 4sectors Concurrent operation: READ from one mem-ory while erasing and writing the other
  256Kbits of SRAM (battery-backed)
  PLD with Macrocells Over 3000 Gates of PLD: CPLD and DPLD CPLD with 16 Output Macrocells (OMCs) and24 Input Macrocells (IMCs) DPLD - user defined internal chip select de-coding
  Seven l/O Ports with 52 I/O pins:52 individually configurable I/O port pins thatcan be used for the following functions: MCU I/OsPLD I/Os Latched MCU address output Special function I/Os l/O ports may be configured as open-drainoutputs
  In-System Programming (ISP) with JTAG Built-in JTAG compliant serial port allows full-chip In-System Programmability Efficient manufacturing allow easy producttesting and programming Use low cost FlashLINK cable with PC
  Page Register Internal page register that can be used to ex-pand the microcontroller address space by afactor of 256
  Programmable power management
  High Endurance: 100,000 Erase/WRITE Cycles of Flash Mem-ory 1,000 Erase/WRITE Cycles of PLD 15 Year Data Retention
  Single Supply Voltage 3V (+20%/10%)
  Memory Speed 100ns Flash memory and SRAM access timefor VCC = 3V (+20%/10%) 90ns Flash memory and SRAM access timefor VCC = 3.3V (+/10%)