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Description: The PSD family of memory systems for microcon-trollers (MCUs) brings In-System-Programmability (ISP) t...


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PSD834F2V General Description


The PSD family of memory systems for microcon-trollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for em-bedded designs. PSD devices combine many of the peripheral functions found in MCU based ap-plications.

The CPLD in the PSD devices features an opti-mized macrocell logic architecture. The PSD mac-rocell was created to address the unique requirements of embedded system designs. It al-lows direct connection between the system ad-dress/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices.

The PSD device includes a JTAG Serial Program-ming interface, to allow In-System Programming (ISP) of the entire device. This feature reduces de- velopment time, simplifies the manufacturing flow,and dramatically lowers the cost of field upgrades.Using ST's special Fast-JTAG programming, a de-sign can be rapidly programmed into the PSD in as little as seven seconds.

The innovative PSD family solves key problems faced by designers when managing discrete Flash memory devices, such as: First-time In-System Programming (ISP)
Complex address decoding
Simulataneous read and write to the device.

The JTAG Serial Interface block allows In-System Programming (ISP), and eliminates the need for an external Boot EPROM, or an external program-
mer. To simplify Flash memory updates, program execution is performed from a secondary Flash memory while the primary Flash memory is being
updated. This solution avoids the complicated hardware and software overhead necessary to im-plement IAP.

ST makes available a software development tool,PSDsoft Express, that generates ANSI-C compli-ant code for use with your target MCU. This code
allows you to manipulate the non-volatile memory (NVM) within the PSD. Code examples are also provided for:
Flash memory IAP via the UART of the host MCU
Memory paging to execute code across several PSD memory pages
Loading, reading, and manipulation of PSD macrocells by the MCU.

PSD834F2V Maximum Ratings

Symbol

Parameter

Min

Max

Unit

TSTG

Storage Temperature

65

125

°C

TLEAD

Lead Temperature during Soldering (20 seconds max.)1

 

235

°C

TLEAD

Input and Output Voltage (Q = VOH or Hi-Z)

0.6

7.0

°C

VIO

Voltage on any Pin

0.6

7.0

V

VCC

Supply Voltage

0.6

14.0

V

VPP

Device Programmer Supply Voltage

0.6

14.0

V

VESD

Electrostatic Discharge Voltage (Human Body model)2

2000

2000

V

PSD834F2V Features

Flash In-System Programmable (ISP)
Peripheral for 8-bit MCUs
3.3 V±10% Single Supply Voltage
2 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 8)
256 Kbit Secondary Flash Memory (4 uniform sectors)
64 Kbit of battery-backed SRAM
Over 3,000 Gates of PLD: DPLD and CPLD
27 Reconfigurable I/O ports
Enhanced JTAG Serial Port
Programmable power management
High Endurance:
100,000 Erase/Write Cycles of Flash Memory
1,000 Erase/Write Cycles of PLD

PSD834F2V datasheet

PSD834F2V
PDF/DataSheet Download

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