Features: • Industry's first TotalCMOSE PLD both CMOS design and process technologies
• Fast Zero Power (FZP TM ) design technique provides ultra-low power and very high speed
• High speed pin-to-pin delays of 10ns
• Ultra-low static power of less than 50mA
• Dynamic power that is 70% lower at 50MHz than competing devices
• 100% routable with 100% utilization while all pins and all macrocells are fixed
• Deterministic timing model that is extremely simple to use
• 4 clocks with programmable polarity at every macrocell
• Support for complex asynchronous clocking
• Innovative XPLATM architecture combines high speed with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5m E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Philips CAE tools
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or product terms in each logic block for:
Programmable 3-State buffer
Asynchronous macrocell register preset/reset
• Programmable global 3-State pin facilitates 'bed of nails' testing without using logic resources
• Available in PLCC, TQFP, and PQFP packages
• Available in both Commercial and Industrial gradesPinout
Specifications
| SYMBOL |
PARAMETER |
MIN. |
MAX. |
Unit |
| VDD |
Supply voltage |
0.5 |
7.0 |
V |
| VI |
Input voltage |
1.2 |
VDD+0.5 |
V |
| VOUT |
Output voltage |
0.5 |
VDD+0.5 |
V |
| IIN |
Input current |
30 |
30 |
mA |
| IOUT |
Output current |
100 |
100 |
mA |
| TJ |
Maximum junction temperature |
40 |
150 |
|
| Tstr |
Storage temperature |
65 |
150 |
|
NOTES:
4. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied.
DescriptionThe PZ3064 CPLD (Complex Programmable Logic Device) is the second in a family of Fast Zero Power (FZP TM ) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZPTM design technique, the PZ3064 offers true pin-to-pin speeds of 10ns, while simultaneously delivering power that is less than 50mA at standby without the need for 'turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD 70% lower at 50MHz. These devices are the first TotalCMOSE PLDs, as they use both a CMOS process technology and the patented full CMOSTM FZPTM design technique. For 5V applications, Philips also offers the high speed PZ5064 CPLD that offers these features in a full 5V implementation.
The Philips FZPTM CPLDs introduce the new patent-pending XPLATM (eXtended Programmable Logic Array) architecture. The XPLATM architecture combines the best features of both PLA and PALTM type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLAE structure in each logic block provides a fast 10ns PALTM path with 5 dedicated product terms per output. This PALE path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 12.5ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.
The PZ3064 CPLDs are supported by industry standard CAE tools (Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either Minc or Philips Semiconductors-developed tools.
The PZ3064 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. PAL is
PZ3064 Data Sheet
