QS532807

·JEDEC compatible LVTTL level
· 10 low skew clock outputs
·  Clock input is 5V tolerant
· Pinout and function compatible with QS5807
·  25W on-chip resistors available for low noise
· Input hysteresis for better noise margin
· Guaranteed low skew:   0.35ns output skew (same bank)   0.6ns output skew (different bank)  0.75ns part-to-part skew
· Available in QSOP and SOIC packages

The QS532807 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532807offers ten non-inverting outputs. Designed in IDT's proprietary QCMOS process, these devices provide low propagation delay buffering with onchip skew of 0.35ns for same-transition, same bank signals. The QS532807 has on-chip series termination resistors for lower noise clock signals. The QS532807 series resistor version is recommended for
driving unterminated lines with capacitive loading and other noise sensitive clock distribution circuits. These clock buffer products are designed for use in high-performance workstations, embedded and personal computing systems. Several devices can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks