Features: - JEDEC compatible LVTTL inputs and outputs- 10 low skew clock outputs (inverting)- Monitor output- Clock inputs are 5V tolerant- Pinout and function compatible with QS5806- Input hysteresis for better noise margin- Guaranteed low skew· 0.6ns output skew (same bank)· 0.8ns output skew (d...
QS53806: Features: - JEDEC compatible LVTTL inputs and outputs- 10 low skew clock outputs (inverting)- Monitor output- Clock inputs are 5V tolerant- Pinout and function compatible with QS5806- Input hysteres...
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Rating |
Symbol |
Max |
unit |
Supply Voltage Range |
V CC1, VCC2 |
0.5 to +4.6
|
V |
Input Voltage Range |
VI (2)
|
0.5 to +5.5 |
V |
Voltage range applied to any output in the high or low state |
VO(2) |
0.5 to VDD + 0.5
|
V |
Input clamp current |
IIK (VI < 0)
|
50 |
mA |
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) |
IOK (VO < 0 or VO > VDD) |
-50
|
mA |
Continuous Output Current |
IRES |
±100 |
mA |
Continuous Current |
VDD or GND |
65 to +150 |
mA |
Junction Temperature |
TSTG |
150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
The QS53806 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS53806 offers banks of five inverting outputs. Designed in IDT's proprietary CMOS process, these devices provide low propagation delay buffering with onchip skew of 0.6ns for same-transition, same-bank signals.