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RF212

Features: • Supports EGSM• LNA and mixer for RF to IF conversion• 12 dB or 20 dB switchable gain step• Minimum 35 dB of image rejection• No external post-LNA filters required• Common Intermediate Frequency (IF) port for all bands• IF range from 350 MHz to ...

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SeekIC No. : 004476190 Detail

RF212: Features: • Supports EGSM• LNA and mixer for RF to IF conversion• 12 dB or 20 dB switchable gain step• Minimum 35 dB of image rejection• No external post-LNA filters re...

RF212 Data Sheet

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Part Number:
RF212
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Supports EGSM
• LNA and mixer for RF to IF conversion
• 12 dB or 20 dB switchable gain step
• Minimum 35 dB of image rejection
• No external post-LNA filters required
• Common Intermediate Frequency (IF) port for all bands
• IF range from 350 MHz to 450 MHz
• High isolation LO input buffer
• Differential IF output
• High dynamic range with low current consumption
• Three-cell battery operation (2.7 to 3.6 V)
• 20-pin Exposed paddle, Thin Shrink Small Outline Package (ETSSOP)


Application

• Dual/tri-band digital cellular mobile telephony
  (EGSM900/DCS1800, or
  EGSM900/DCS1800/PCS1900)


Pinout

Connection Diagram


Specifications

Parameter Minimum Maximum Units
Storage Temperature 40 +125 °C
Supply Voltage (VCC) 0.3 +3.6 V
Input Voltage Range 0.3 Vcc V



Description

The RF212 device is available as a dual-band (EGSM900/DCS1800) front end or as a tri-band (EGSM900/DCS1800/PCS1900) front end for Global System for Mobile Communications (GSM) mobile telephony applications. Each device of RF212 integrates all the required front-end components after the frequency pre-select filters. These components include the Low Noise Amplifiers (LNAs), the internal image-reject filters, mixers, and a Local Oscillator (LO) amplifier.

The main advantage of the RF212 is its ability to provide a minimum of 35 dB of image rejection for each band. The block diagrams of the devices are shown in Figures 1 and 2. The device packages and pin configurations are shown in Figures 3 and 4.




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