RM5230

The RM5230 has the following features including High-performance floating-point unit:Single cycle repeat rate for common single precision operations and some double precision operations,Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations,Single cycle repeat rate for single precision combined multiply-add operation;MIPS IV instruction set:Floating-point multiply-add instruction increases performance in signal processing and graphics applications,Conditional moves to reduce branch frequency,Index address modes (register+reg iste r);Embedded application enhancements:Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction,I and D cache locking by set,Optional dedicated exception vector for interrupts;Fully static CMOS design with power down logic:Standby reduced power mode with WAIT instruction,2.5 Watts typical with less than 70 mA standby current  128-pin Power-Quad 4 package.

The RM5230 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM5230 are briefly described below.The RM5230 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high-throughput fully pipelined floating-point execution unit, the superscalar capability of the RM5230 provides unparalleled price/performance in computational intensive embedded applications.Like all MIPS ISA processors, the RM5230 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. Figure 1 shows the user visible state.

For integer operations, loads, stores, and other non-floating-point operations, the RM5230 uses the simple 5-stage pipeline also found in the 84600, 84700, and 85000 devices. In addition to this standard pipeline, it uses an extended 7-stage pipeline for floating-point operations. Like the 85000, it does virtual to physical translation in parallel with cache access.