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RM5231A

Features: • Dual Issue superscalar microprocessor• 250, 300, and 350 MHz operating frequencies• Up to 420 Dhrystone 2.1 MIPS• System interface optimized for embedded applications• 32-bit system interface lowers total system cost• High-performance write protocols...

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RM5231A: Features: • Dual Issue superscalar microprocessor• 250, 300, and 350 MHz operating frequencies• Up to 420 Dhrystone 2.1 MIPS• System interface optimized for embedded applicat...

RM5231A Data Sheet

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Part Number:
RM5231A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Dual Issue superscalar microprocessor
• 250, 300, and 350 MHz operating frequencies
• Up to 420 Dhrystone 2.1 MIPS
• System interface optimized for embedded applications
• 32-bit system interface lowers total system cost
• High-performance write protocols maximize uncached write bandwidth
• Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• IEEE 1149.1 JTAG boundary scan
• Integrated on-chip caches
• 32 KB instruction and 32 KB data - 2 way set associative
• Per set locking
• Virtually indexed, physically tagged
• Write-back and write-through on a per page basis
• Pipeline restart on first doubleword for data cache misses
• Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 48 dual entries map 96 pages
• Variable page size (4 KB to 16 MB in 4x increments)
• High-performance floating-point unit - up to 700 MFLOPS
• Single cycle repeat rate for common single-precision operations and some double precision operations
• Two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations
• Single cycle repeat rate for single-precision combined multiply-add operation
• MIPS IV instruction set
• Floating point multiply-add instruction increases performance in signal processing and graphics applications
• Conditional moves to reduce branch frequency
• Index address modes (register + register)
• Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction
• I and D cache locking by set
• Optional dedicated exception vector for interrupts
• Fully static 0.18 micron CMOS design with power down logic
• Standby reduced power mode with WAIT instruction
• 1.65 V or 1.8 V core with 3.3 V or 2.5 V I/O
• 128-pin QFP package




Specifications

Symbol Rating Limits Unit
VTERM Terminal Voltage with respect to GND 0.52 to+3.9 V
TCASE Operating Temperature
Commercial 0 to +85
Industrial 45 to +85
TSTG Storage Temperature 55 to +125
IIN DC Input Current ±203 mA
IOUT DC Output Current ±204 mA
Notes
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 Volts.
3. When VIN < 0V or VIN > VccIO.
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.




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