S-70L41B

The S-70L41B is a kind of fully integrated CMOS POCSAG (CCIR Radio Paging code No.1) decoder and page controller for display pagers which also has an improved synchronization algorithm for efficient power saving. The decoded POCSAG data are transferred over a serial interface to a microcontroller according to its commands for processing and subsequent storage and display. Its on chip buffer register allows the microcontroller to stay in subclock (lower frequency) mode in receiving interrupt requests from S70L41B. In addition to its conventional decoding and error correcting function, it has a data conversion function for Chinese characters. With 76.8kHz X'tal oscillator, the decoder can be applied to any one of 512,1200 and 2400 bps system by using its internal registers.

The features of S-70L41B can be summarized as (1)low voltage operation 0.9Vmin; (2)low current consumption 50A max. @1.5V; (3)8bit serial interface for a CPU with on-chip level shifters; (4)data conversion function (data lenghth of 4, 7 or 8 bits); (5)512/1200/2400bps register selectable; (6)6 addresses and two frames (programmable address assignment); (7)programmable receiver warm-up's .

The absolute maximum ratings of s-S-70L41B are (1)supply voltage VCC: -0.3 to 4.5V; (2)input voltage VIN: VSS-0.3 to VDD + 0.3V; (3)output voltage VOUT: VSS to VDDV; (4)storage temperature Tbias: -40 to + 125°C; (5)operating temperature Topr: -10 to + 50°C.