S1L50000

Features:

` Process         0.35m 2/3/4 layer metalization CMOS process
` Integration    A maximum of 815,468 gates (2 input NAND gate equivalent)
` Operating Speed       Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ) (2-input pair NAND, F/O = 2, Typical wire load)
                                    Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used. 400 ps (3.3V Typ), 1.30 ns (2.0V Typ) (F/O = 2, Typical wire load)
                                    Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used. 2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ) (CL = 15 pF)
` I/F Levels      Input/Output TTL/CMOS/LVTTL compatible
` Input Modes  TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI Built-in pull-up and pull-down resistors can be usable. (2 types for each resistor value)
` Output Modes Normal, 3-state, bi-directional, PCI
` Output Drive IOL = 0.1, 1, 3, 8, 12, 24 mA selectable (Built-in level shifter is used at 5.0V)
     I<sub>OL</sub> = 0.1, 1, 2, 6, 12 mA selectable (at 3.3V)
     I<sub>OL</sub> = 0.05, 0.3, 0.6, 2, 4 mA selectable (at 2.0V)
` RAM Asynchronous 1-port, asynchronous 2-port
` Dual Power Operation supported by using level-shifter circuit
     Internal logic: Operation supported by low voltage
     I/O Buffer: Built-in interfaces of both high and low voltages possible
` Operation possible at V_DD= 2.0 ± 0.2V


Specifications

Item	Symbol	Limits	Unit
Power Supply Voltage	VDD	-0.3 to 4.0	V
Input Voltage	VI	-0.3 to VDD + 0.5*1	V
Output Voltage	VO	-0.3 to VDD + 0.5*1	V
Output Current/Pin	IOUT	± 30	mA
Storage Temperature	TSTG	-65 to 150	°C

*1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH systems.

Item	Symbol	Limits	Unit
Power Supply Voltage	HVDD	-0.3 to 7.0	V
	LVDD	-0.3 to 4.0	V
Input Voltage	HVI	-0.3 to HVDD + 0.5*1	V
	LVI	-0.3 to LVDD + 0.5*1	V
Output Voltage	HVO	-0.3 to HVDD + 0.5*1	V
	LVO	-0.3 to LVDD + 0.5*1	V
Output Current/Pin	IOUT	± 30 (± 50 *2)	mA
Storage Temperature	TSTG	-65 to 150	°C

**1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH systems.
*2: Possible to use for 24mA of output buffer.

 

Description

EPSON Electronics America, Inc.'s S1L50000 Series is a family of ultra high-speed VLSI CMOS gate array utilizing a 0.35mm "sea-of-gates" architecture. The S1L50000H products feature 5V tolerant I/O buffers.
` Ultra-high-speed, high density and low power consumption
` Low voltage operation: 3.3V and 2.0V
` Number of raw gates: 28,710 ~ 815,468 gates