Features: Software command-set compatible with JEDEC 42.4 standard Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDLfamilies and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDLfamiliesCFI (Common Flash Interface) compliant Provides device-specific information to the system, allowing hostsoftware...
S29PL-J: Features: Software command-set compatible with JEDEC 42.4 standard Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDLfamilies and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDLfamiliesCFI (Common ...
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| Storage Temperature Plastic Packages |
65°C to +150°C |
| Ambient Temperature with Power Applied |
65°C to +125°C |
| Voltage with Respect to Ground | |
| VCC (Note 1) |
0.5 V to +4.0 V |
| A9, OE#, and RESET# (Note 2) |
0.5 V to +13.0 V |
| WP#/ACC (Note 2) |
0.5 V to +10.5 V |
| All other pins (Note 1) |
0.5 V to VCC +0.5 V |
| Output Short Circuit Current (Note 3) |
200 mA |
S29PL-J features:
128/128/64/32 Mbit Page Mode devices
Page size of 8 words: Fast page read access from random locations
within the page
Single power supply operation
Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations
for battery-powered applications
Dual Chip Enable inputs (only in PL129J)
Two CE# inputs control selection of each half of the memory space
Simultaneous Read/Write Operation
Data can be continuously read from one bank while executing erase/
program functions in another bank
Zero latency switching from write to read operations
FlexBank Architecture (PL127J/PL064J/PL032J)
4 separate banks, with up to two simultaneous operations per device
Bank A:
PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
Bank B:
PL127J - 48 Mbit (32 Kw x 96)
PL064J - 24 Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
Bank C:
PL127J - 48 Mbit (32 Kw x 96)
PL064J - 24 Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
Bank D:
PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
FlexBank Architecture (PL129J)
4 separate banks, with up to two simultaneous operations per device
CE#1 controlled banks:
Bank 1A: PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B: PL129J - 48Mbit (32Kw x 96)
CE#2 controlled banks:
Bank 2A: PL129J - 48 Mbit (32Kw x 96)
Bank 2B: PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
Enhanced VersatileI/O (VIO) Control
Output voltage generated and input voltages tolerated on all control
inputs and I/Os is determined by the voltage on the VIO pin
VIO options at 1.8 V and 3 V I/O for PL127J and PL129J devices
3V VIO for PL064J and PL032J devices
Secured Silicon Sector region
Up to 128 words accessible through a command sequence
Up to 64 factory-locked words
Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector typical